SLUUDH6 April   2026 CC3501E , CC3551E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations - CC35xxE IC
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
        1. 2.2.1.1 LDO Recommendations
      2. 2.2.2 Boot Sequence
        1. 2.2.2.1 Hosted Mode (Power up by reset pin)
        2. 2.2.2.2 Standalone Mode (Power up when supply above threshold)
        3. 2.2.2.3 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
        3. 2.3.2.3 Slow Clock Using an External Crystal (XTAL)
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 xSPI
        1. 2.5.1.1 External Serial Flash
      2. 2.5.2 Serial Wire Debug (SWD)
      3. 2.5.3 Logger
      4. 2.5.4 Coexistence
    6. 2.6 Stacked PSRAM Variant
  6. 3Layout Considerations - CC35xxE IC
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design - CC355xE Dual Band Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 External Flash Layout

3.6 External Flash Layout

The external flash provides programmable, nonvolatile program memory for the device. Up to 64MB of flash memory is supported. Using the external flash allows the user to use saved network-specific data and avoids the need for a full start-up and network find-and-join process. The CC35xxE device communicates to the external flash using xSPI.

The xSPI lines include xSPI_CLK, xSPI_CS_FLASH, xSPI_D0, xSPI_D1, xSPI_D2, and xSPI_D3. The xSPI_CLK signal in particular is very sensitive and should be regarded as such. In order to ensure reliable xSPI communication, the following layout considerations should be taken into account:

  • Trace Length should be no more than 1000 mil (25.4 mm)
  • The lengths of the traces must be length matched within 100 mil tolerance to provide the sampled data at the same time on all of the traces.

Figure 3-10 is sampled from the LP-EM_CC35X1 design files.

CC35xxE External Serial Flash Figure 3-10 CC35xxE External Serial Flash