SLUUDH6 April   2026 CC3501E , CC3551E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations - CC35xxE IC
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
        1. 2.2.1.1 LDO Recommendations
      2. 2.2.2 Boot Sequence
        1. 2.2.2.1 Hosted Mode (Power up by reset pin)
        2. 2.2.2.2 Standalone Mode (Power up when supply above threshold)
        3. 2.2.2.3 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
        3. 2.3.2.3 Slow Clock Using an External Crystal (XTAL)
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 xSPI
        1. 2.5.1.1 External Serial Flash
      2. 2.5.2 Serial Wire Debug (SWD)
      3. 2.5.3 Logger
      4. 2.5.4 Coexistence
    6. 2.6 Stacked PSRAM Variant
  6. 3Layout Considerations - CC35xxE IC
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design - CC355xE Dual Band Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 External Flash Layout

2.2.2.2 Standalone Mode (Power up when supply above threshold)

CC35xxE device is the host in your system and not controlled by external MCU. In this configuration the following boot-up sequence should be followed:

Power Up by When Supply Above Threshold

In this configuration the VDD_ANA_IN pin and reset pin needs to be shorted to the VDD_MAIN_IN pin. The VDDSF needs to be shorted to either VDD_MAIN or VIO1 or VIO2. When nRESET is shorted to the VMAIN supply, the CC35xxE device will recognize when the supply is stable (within recommended operating conditions). However, user must ensure that the VPA supply is within recommended operating conditions before enabling device either:

  • 1ms after VDDMAIN/VIO/VDDSF are available
  • Prior to or as soon as VDDMAIN is available

It is important to note:

  • When either VIO1, VIO2, or VDDSF is 3.3V, it is important to ensure that the 3.3V is available <15ms after VDDMAIN reaches 1.8V. It is expected this will be the normal case in systems where the 1.8V supply is derived from the 3.3V supply.
  • When reset is driven from an external source, it can be driven from 1.8V or 3.3V IO independently of VIO1 level.

Figure 2-3 shows the top-level block diagram for the CC35xxE in both configurations

CC35xxE Configuration Options Figure 2-3 CC35xxE Configuration Options