SLUUDH6 April 2026 CC3501E , CC3551E
For optimal power consumption, the slow clock can be generated externally by an oscillator, XTAL, or sourced from elsewhere in the system. If using an oscialltor, the external source must meet the requirements listed below. This clock should be fed into the CC35xxE pin Slow_CLK_IN/ GPIO0 and should be stable before nReset is deasserted and device is enabled. The clock signal logic high should be the same voltage as VIO1 IO Ring.
| Parameter | Description | MIN | TYP | MAX | Unit | |
|---|---|---|---|---|---|---|
| Input slow clock frequency | Square wave | 32.768 | kHz | |||
| Frequency accuracy | Inital + temperature + aging | ±250 | ppm | |||
| Input Duty cycle | 30% | 50% | 70% | |||
| Tr/Tf | Rise and fall time | 10% to 90% (rise) and 90% to 10% (fall) of digital signal level | 100 | ns | ||
| Input impedence | 1 | MΩ | ||||
| Input capacitance | 5 | pF | ||||