SLUUDH6 April   2026 CC3501E , CC3551E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations - CC35xxE IC
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
        1. 2.2.1.1 LDO Recommendations
      2. 2.2.2 Boot Sequence
        1. 2.2.2.1 Hosted Mode (Power up by reset pin)
        2. 2.2.2.2 Standalone Mode (Power up when supply above threshold)
        3. 2.2.2.3 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
        3. 2.3.2.3 Slow Clock Using an External Crystal (XTAL)
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 xSPI
        1. 2.5.1.1 External Serial Flash
      2. 2.5.2 Serial Wire Debug (SWD)
      3. 2.5.3 Logger
      4. 2.5.4 Coexistence
    6. 2.6 Stacked PSRAM Variant
  6. 3Layout Considerations - CC35xxE IC
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design - CC355xE Dual Band Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 External Flash Layout

3.5 Power Supplies

The power supplies, ground traces, and the decoupling capacitors are important for having an optimal layout. Since the decoupling capacitors can be close to the RF pins and traces of the device and power supplies, traces must be thick enough to support the necessary current to the device.

  • PA_LDO_OUT (pin 1): It is suggested to have the decoupling capacitor close to the device pin, as well as a thick enough trace to have a low impedance path to the capacitor. For a visual representation, see Figure 3-8.
  • VDD_ANA_IN1 and VDD_ANA_IN2 (pins 4 and 5): The supply side of the decoupling capacitors must be shorted together with a polygon region with two power vias (one for each decoupling capacitor). The ground side of each capacitor must go directly to ground by separate vias (not shorted together), and be isolated from the rest of the ground plane on the top layer.
  • For the 1.8V power delivery, a thick trace or power plane must be used to carry the required amount of current consumption in VDD_MAIN_IN, VDD_ANA_IN1, VDD_ANA_IN2, and VPP_IN combined.
  • VDD_DIG_IN (pin 10) and DIG_LDO_OUT (pin 47) must be shorted together on a layer that is not the top layer or ground layer (place it on layer 3 or 4).This way the power path cannot interrupt the RF trace on top layer (layer 1) or the continuous ground layer (layer 2). For a visual reference, see Figure 3-9. The decoupling capacitor should be close to pin 47.
  • VDDSF (pin 23) must be configured to 1.8V. A thick trace or power plane must be used to carry the required amount of current consumption.
  • VIO1 (pin 37) and VIO2 (pin 15) can be configured to 1.8V or 3.3V. A thick trace or power plane must be used to carry the required amount of current consumption.
  • The 1.8V path must be located around the device on a layer that is not the top layer or ground layer (place it on layer 3 or 4). This way the power path cannot interrupt the RF trace on top layer (layer 1) or the continuous ground layer (layer 2). Only one via is used for each 1.8V power supply, the 1.8V supply currents must not flow under the device.
  • For the 3.3V power delivery, a thick trace or a power plane must be used to carry the required amount of current consumption of the PA_LDO_IN. The power delivery must also be placed on a layer that is not top layer or ground layer (layer 3 or 4).
  • PA_LDO_IN (pins 55 and 56): These two pins must be shorted together with a solid region. The decoupling capacitor should be placed close to the device. Use two vias if possible to deliver the 3.3V rail.

Figure 3-8 is sampled from the LP-EM-CC35X1 design files.

Reference Layout of CC35xxE Power Supplies Figure 3-8 Reference Layout of CC35xxE Power Supplies

Figure 3-9 is sampled from the LP-EM-CC35X1 design files.

Reference Layout of the Power Layer (Layer 3) Figure 3-9 Reference Layout of the Power Layer (Layer 3)