SLVK222 August   2025 TPS7H5020-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. Introduction
  5. Single-Event Effects (SEE)
  6. Device and Test Board Information
  7. Irradiation Facility and Setup
  8. LETEFF and Range Calculation
  9. Test Setup and Procedures
  10. Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. Single-Event Transients (SET)
  12. Event Rate Calculations
  13. 10Summary
  14.   A References

Test Setup and Procedures

There were two input supplies used to power the TPS7H502X-SP which provided VIN and EN. The VIN for the device was provided via Ch. 3 of an N6705C power module and ranged from 4.5V to 14V for SEL, SEB/SEGR, and SET testing. The EN of the device was driven by an E36311A power supply and was either forced to 0V or 4.5V to enable or disable the device. A NI PXIe-6341 DAQ was used to drive VSNS and VCOMP. VLDO had 3 programmable voltages, 4.5V, 5V, or 5.5V and were selected by closing relays to connect to a feedback network on the EVM to select the required VLDO voltage. Input ranges for the different modes and switching frequencies are shown below. Note that the PVIN column denotes whether or not PVIN (the driver stage input) was tied to VIN or VLDO.

Table 6-1 TPS7H502X-SP Mode Bias Ranges

Mode

VIN (V)

PVIN

VLDO (V)

VSNS (V)

VCOMP (V)

EN (V)

RT (Ω)

FSW (Hz)

Silicon

4.5-14

VIN

4.5-5.5

0.6

0.8

0/4.5

205k

500k

4.5-14

VIN

4.5-5.5

0.6

1.45

0/4.5

1.07M

100k

4.5-14

VIN

4.5-5.5

0.6

0.6

0/4.5

90.9k

1M

GaN

4.5-14

VLDO

4.5-5.5

0.6

0.6

0/4.5

205k

500k

4.5-14

VLDO

4.5-5.5

0.6

0.925

0/4.5

1.07M

100k

4.5-14

VLDO

4.5-5.5

0.6

0.45

0/4.5

90.9k

1M

The primary signal monitored during testing was GATE (OUTH and OUTL tied together on the EVM) and this was done so using a PXIe-5110 triggering using a pulse-width trigger at 20%. The other three signals monitored were REFCAP, VLDO, and SS which were monitored on their own independent NI PXIe-5172 or NI PXIe-5162 cards. The two signals on the PXIe-5172 triggered on a 3% window, the SS signal triggered off of 500-mV below its nominal value.

All equipment was controlled and monitored using a custom-developed LabVIEW™ program (PXI-RadTest) running on a HP-Z4 desktop computer. The computer communicates with the PXI chassis via an MXI controller and NI PXIe-8381 remote control module.

Equipment Settings and Parameters Used During the Open-Loop SEE Testing of the TPS7H502X-SP shows the connections, limits, and compliance values used during the testing. Figure 6-1 shows a block diagram of the setup used for SEE testing of the TPS7H502X-SP.

Note that only the relay for the correct feedback network was driven by the PXIe-6341 for VLDO, not the actual VLDO voltage.

Table 6-2 Equipment Settings and Parameters Used During the Open-Loop SEE Testing of the TPS7H502X-SP
PIN NAME EQUIPMENT USED CAPABILITY COMPLIANCE RANGE OF VALUES USED
VIN N6705C

(CH # 3)

20.4V, 50A 5A 2.5 to 7V

EN

E36311A (CH # 1)

5V,5A

0.1A

0V, 5V

VSNS

PXIe-6341

±10V, ±5mA

N/A

0.6V

VCOMP

PXIe-6341

±10V, ±5mA

N/A

0.45V to 1.45V

VLDO

PXIe-6341 ±10V, ±5mA N/A

0V, 5V

GATE

PXIe-5110

100 MS/s

100 MS/s

REFCAP

PXIe-5172 100 MS/s 100 MS/s

VLDO

PXIe-5172 (2)

100 MS/s

100 MS/s

SS

PXIe-5162 5 GS/s 100 MS/s

For testing of the TPS7H502X-SP in the flyback configuration VIN was set to 12V and supplied through Ch. 1 of the N6705C. The input of the power stage was set to 28V and supplied through Ch. 3 of the N6705C. The programmable VLDO was set to 5V. For all flyback configuration testing PVIN was tied to VLDO putting the device in GaN mode. A Chroma E-Load in constant resistance mode was used to load the device with a resistance of 1.25Ω to provide a load of 4A. The primary signals monitored were GATE (the OUTH and OUTL tied together before the transformer) and VOUT (the DC output after the transformer).

Table 6-3 Equipment Settings and Parameters Used During the Flyback Configuration SEE Testing of the TPS7H502X-SP
PIN NAME EQUIPMENT USED CAPABILITY COMPLIANCE RANGE OF VALUES USED
VIN

(V)

N6705C

(CH # 1)

20.4V, 50A 10A 12V

Power Stage (V)

N6705C

(CH # 3)

60V, 17.2A

10A

28V

GATE

PXIe-5110

100 MS/s

100MS/s

VOUT

PXIe-5172 100 MS/s 100 MS/s

VOUT

Chroma E36300

80A

Low

1.25Ω

All boards used for SEE testing were fully checked for functionality. Dry runs were also performed to ensure that the test system was stable under all bias and load conditions prior to being taken to the test facilities. During the heavy-ion testing, the LabVIEW control program powered up the TPS7H502X-SP device and set the external sourcing and monitoring functions of the external equipment. After functionality and stability was confirmed, the beam shutter was opened to expose the device to the heavy-ion beam. The shutter remained open until the target fluence was achieved (determined by external detectors and counters). During irradiation, the NI scope cards continuously monitored the signals. When the output exceeded the pre-defined pulse-width or window trigger, a data capture was initiated. No sudden increases in current were observed (outside of normal fluctuations) on any of the test runs and indicated that no SEL or SEB/SEGR events occurred during any of the tests.

 Block Diagram of the SEE Test
                    Setup for the TPS7H502X-SP Figure 6-1 Block Diagram of the SEE Test Setup for the TPS7H502X-SP