SLVK222 August   2025 TPS7H5020-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 LETEFF and Range Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References

3 Device and Test Board Information

The TPS7H502X-SP is packaged in a 24-pin HTSSOP PWP plastic package as shown in Figure 3-1. A custom TPS7H502X-SP evaluation module, designed for open-loop SEE testing and the TPS7H5020FLYEVM-CVAL, used for flyback SEE testing, were used to evaluate the performance and characteristics of the TPS7H502X-SP under heavy ion radiation. The evaluation modules are shown in Figure 3-2 and . The schematics are shown in Figure 3-3.

Photograph of Delidded TPS7H502X-SP [Left] and Pinout Diagram [Right]Figure 3-1 Photograph of Delidded TPS7H502X-SP [Left] and Pinout Diagram [Right]
Note: The package was delidded/decapped to reveal the die face for all heavy-ion testing.
TPS7H502X-SP Custom EVM Top ViewFigure 3-2 TPS7H502X-SP Custom EVM Top View
TPS7H502X-SP Custom EVM Controller Schematic Figure 3-3 TPS7H502X-SP Custom EVM Controller Schematic
TPS7H502X-SP Custom EVM Auxiliary Schematic Figure 3-4 TPS7H502X-SP Custom EVM Auxiliary Schematic
TPS7H5020FLYEVM-EVAL Top View Figure 3-5 TPS7H5020FLYEVM-EVAL Top View
TPS7H5020FLYEVM-CVAL Controller Schematic Figure 3-6 TPS7H5020FLYEVM-CVAL Controller Schematic
TPS7H5020FLYEVM-CVAL Power Stage Schematic Figure 3-7 TPS7H5020FLYEVM-CVAL Power Stage Schematic