SLVS647J August   2006  – May 2025 TLE4275-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power-Good Reset (RESET)
      2. 7.3.2 Adjustable Power-Good RESET Delay Timer (DELAY)
        1. 7.3.2.1 Setting the Adjustable Power-Good Reset Delay
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
        1. 8.1.1.1 Legacy Chip Capacitor Selection
        2. 8.1.1.2 New Chip Capacitor Selection
          1. 8.1.1.2.1 Output Capacitor
          2. 8.1.1.2.2 Input Capacitor
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 Setting the Adjustable Power-Good Reset Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TLE4275-Q1 KVU Package, 5-Pin TO-252 (Top View)Figure 4-1 KVU Package, 5-Pin TO-252 (Top View)
TLE4275-Q1 PWP Package, 20-Pin HTSSOP (Top View, Legacy Chip)Figure 4-3 PWP Package, 20-Pin HTSSOP (Top View, Legacy Chip)
TLE4275-Q1 KTT Package, 5-Pin DDPAK/TO-263 (Top View)Figure 4-2 KTT Package, 5-Pin DDPAK/TO-263 (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME KVU KTT PWP
DELAY 4 4 3 I Reset (power-good) delay adjustment pin. Connect a capacitor from this pin to GND to set the PG reset delay. Leave this pin floating for a default (t(DLY_FIX)) delay. See the Power-Good Reset (RESET) section for more information. If RESET/DELAY functionality is not desired, leave this pin floating because connecting this pin to GND causes a permanent increase in the GND current.
GND 3 3 8 G Ground reference.
IN 1 1 19 P Input power-supply voltage pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to GND. See the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the input of the device as possible.
NC — — 2, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20 — No internal connection. This pin can be left floating, or connected to GND for best thermal performance
OUT 5 5 4 O Regulated output voltage pin. A capacitor is required from OUT to GND for stability. Increasing the output capacitance from the minimum value required for stability results in improved transient response. See the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible. If using a high equivalent series resistance (ESR) capacitor, decouple the output with a 100nF ceramic capacitor.
RESET 2 2 1 I Reset (power-good) pin with active-high functionality. An open-drain output indicates when the output voltage reaches VPG(TH,RISING) of the target. Using a feed-forward capacitor disrupts RESET functionality. See the Power-Good Reset (RESET) section for more information.
Thermal pad Pad Pad Pad — Connect the thermal pad to a large area GND plane for improved thermal performance.
(1) I = input; O = output; P = power; G = ground.