SLVS647J August   2006  – May 2025 TLE4275-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power-Good Reset (RESET)
      2. 7.3.2 Adjustable Power-Good RESET Delay Timer (DELAY)
        1. 7.3.2.1 Setting the Adjustable Power-Good Reset Delay
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
        1. 8.1.1.1 Legacy Chip Capacitor Selection
        2. 8.1.1.2 New Chip Capacitor Selection
          1. 8.1.1.2.1 Output Capacitor
          2. 8.1.1.2.2 Input Capacitor
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 Setting the Adjustable Power-Good Reset Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

specified at TJ = –40°C to +150°C, VIN = 13.5V, IOUT = 0 mA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, CIN = 1µF,  typical values are at TJ = 25°
PARAMETER Test Conditions MIN TYP MAX UNIT
VOUT Output voltage VIN = 6V to 28V, IOUT = 5mA to 400mA 4.9 5 5.1 V
VIN = 6V to 40V, IOUT = 5mA to 200mA 4.9 5 5.1
IO Output current limit 450 700 950 mA
ΔVOUT(ΔIOUT) Load regulation (for legacy chip) IOUT = 5mA to 400mA 15 30 mV
Load regulation (for new chip) IOUT = 5mA to 400mA, VIN = 6V 15 30
ΔVOUT(ΔVIN) Line regulation (for legacy chip) VIN = 8V to 32V,  IOUT = 5mA –15 5 15 mV
Line regulation (for new chip) VIN = 6V to 40V,  IOUT = 5mA –15 5 15
IQ Current consumption, IQ = IIN – IOUT (for legacy chip) IOUT = 1mA TJ = 25ºC 150 200 µA
TJ ≤ 85ºC 150 220
Current consumption, IQ = IIN – IOUT (for new chip) TJ = 25ºC 28 50
TJ ≤ 85ºC 28 55
Current consumption, IQ = IIN – IOUT IOUT = 250mA 5 10 mA
IOUT = 400mA 12 22
VDO Dropout voltage IOUT = 300mA, VDO = VIN – VOUT 250 500 mV
VUVLO(RISING) Rising input supply UVLO (for new chip) VIN rising 2.6 2.7 2.82 V
VUVLO(FALLING) Falling input supply UVLO (for new chip) VIN falling 2.38 2.5 2.6 V
VUVLO(HYST) V UVLO(IN) hysteresis (for new chip) 230 mV
PSRR Power-supply rejection ratio frequency = 100Hz, Vr = 0.5 Vpp 60 dB
ΔVOUT/ΔT Temperature output voltage drift 0.5 mV/K
VRESET(OL) RESET (PG) pin low-level output voltage (for legacy chip) Rext ≥ 5kΩ, VOUT > 1V 0.2 0.4 V
RESET (PG) pin low-level output voltage (for new chip) Rext ≥ 5kΩ, 1V ≤ VOUT < 4.5V 0.2 0.4
VOUT(RT) RESET (PG) switching threshold (for legacy chip) 4.5 4.65 4.8 V
RESET (PG) switching threshold (for new chip) VOUT rising 4.25 4.75
IROH RESET output leakage current VROH = 5V 0 10 µA
IDLY(CHARGE) RESET charging current (for legacy chip) Voltage at DELAY pin = 1V 3 5.5 9 µA
RESET charging current (for new chip) 1 1.5 2
VDELAY_U (TH) RESET upper timing threshold (for legacy chip) Voltage at DELAY pin rising 1.5 1.8 2.2 V
RESET upper timing threshold (for new chip) Voltage at DELAY pin rising 1.17 1.21 1.25
VDELAY_RL (TH) RESET lower timing threshold (for legacy chip) Voltage at DELAY pin rising 0.2 0.4 0.7 V
TSD(SHUTDOWN) Junction shutdown temperature (for new chip) 175 °C
TSD(HYST) Hysteresis of thermal shutdown (for new chip) 20 °C