SLVS647J August   2006  – May 2025 TLE4275-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power-Good Reset (RESET)
      2. 7.3.2 Adjustable Power-Good RESET Delay Timer (DELAY)
        1. 7.3.2.1 Setting the Adjustable Power-Good Reset Delay
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
        1. 8.1.1.1 Legacy Chip Capacitor Selection
        2. 8.1.1.2 New Chip Capacitor Selection
          1. 8.1.1.2.1 Output Capacitor
          2. 8.1.1.2.2 Input Capacitor
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 Setting the Adjustable Power-Good Reset Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.4 Thermal Information

THERMAL METRIC (1) TLE4275-Q1 UNIT
KVU
(TO-252-5)		 KTT
(TO-263-5)		 PWP
(HTSSOP-20)
Legacy Chip New Chip Legacy Chip New Chip Legacy Chip
RθJA Junction-to-ambient thermal resistance 40.3 28.6 32.8 22.5 39.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.8 36.3 38.0 7.2 22.7 °C/W
RθJB Junction-to-board thermal resistance 17.2 7.3 5.3 32.3 19.1 °C/W
ψJT Junction-to-top characterization parameter 2.8 1.8 6.3 2.0 0.6 °C/W
ψJB Junction-to-board characterization parameter 17.1 7.2 5.4 3.4 18.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 0.7 0.8 6.8 1.5 °C/W
(1) The thermal data is based on the JEDEC standard high K profile, JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper. The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.