SLVSHC8 May   2023 DRV8334-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions 48-Pin DRV8334-Q1
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 3x PWM Mode with SPI enable control
          4. 6.3.1.1.4 1x PWM Mode
          5. 6.3.1.1.5 SPI Gate Drive Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 GVDD Charge pump/LDO
          3. 6.3.1.2.3 VCP Trickle Charge pump
          4. 6.3.1.2.4 Gate Driver Output
          5. 6.3.1.2.5 Passive and Semi-active pull-down resistor
          6. 6.3.1.2.6 TDRIVE Gate Drive Timing Control
          7. 6.3.1.2.7 Propagation Delay
          8. 6.3.1.2.8 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 Low-Side Current Sense Amplifiers
        1. 6.3.2.1 Unidirectional Current Sense Operation
        2. 6.3.2.2 Bidirectional Current Sense Operation
      3. 6.3.3 Gate Driver Shutdown
        1. 6.3.3.1 DRVOFF Gate Driver Shutdown
        2. 6.3.3.2 Gate Driver Shutdown Timing Sequence
      4. 6.3.4 Gate Driver Protective Circuits
        1. 6.3.4.1  PVDD Supply Undervoltage Warning (PVDD_UVW)
        2. 6.3.4.2  PVDD Supply Undervoltage Lockout (PVDD_UV)
        3. 6.3.4.3  PVDD Supply Overvoltage Fault (PVDD_OV)
        4. 6.3.4.4  GVDD Undervoltage Lockout (GVDD_UV)
        5. 6.3.4.5  GVDD Overvoltage Fault (GVDD_OV)
        6. 6.3.4.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.4.7  BST Overvoltage Fault (BST_OV)
        8. 6.3.4.8  VCP Undervoltage Fault (CP_OV)
        9. 6.3.4.9  VCP Overvoltage Fault (CP_OV)
        10. 6.3.4.10 VDRAIN Undervoltage Fault (VDRAIN_UV)
        11. 6.3.4.11 VDRAIN Overvoltage Fault (VDRAIN_OV)
        12. 6.3.4.12 MOSFET VGS Monitoring Protection
        13. 6.3.4.13 MOSFET VDS Overcurrent Protection (VDS_OCP)
        14. 6.3.4.14 VSENSE Overcurrent Protection (SEN_OCP)
        15. 6.3.4.15 Phase Comparators
        16. 6.3.4.16 Thermal Shutdown (OTSD)
        17. 6.3.4.17 Thermal Warning (OTW)
        18. 6.3.4.18 OTP CRC
        19. 6.3.4.19 SPI Watchdog Timer
        20. 6.3.4.20 Phase Diagnostic
    4. 6.4 Device Functional Modes
      1. 6.4.1 Gate Driver Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Operating Mode
      2. 6.4.2 Device Power Up Sequence
    5. 6.5 Programming
      1. 6.5.1 SPI
      2. 6.5.2 SPI Format
      3. 6.5.3 SPI Format Diagrams
  8. 7 Register Maps
    1. 7.1 STATUS Registers
    2. 7.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
      2. 8.2.2 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.2 CONTROL Registers

Table 7-9 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in Table 7-9 are considered as reserved locations and the register contents are not to be modified.

Table 7-9 CONTROL Registers
AddressAcronymRegister NameSection
1AhIC_CTRL1IC Control Register 1Section 7.2.1
1BhIC_CTRL2IC Control Register 2Section 7.2.2
1ChIC_CTRL3IC Control Register 3Section 7.2.3
1EhGD_CTRL1Gate Drive Control Register 1Section 7.2.4
1FhGD_CTRL2Gate Drive Control Register 2Section 7.2.5
21hGD_CTRL3Gate Drive Control Register 3Section 7.2.6
22hGD_CTRL3BGate Drive Control Register 3BSection 7.2.7
23hGD_CTRL4Gate Drive Control Register 4Section 7.2.8
24hGD_CTRL5Gate Drive Control Register 5Section 7.2.9
25hGD_CTRL6Gate Drive Control Register 6Section 7.2.10
26hGD_CTRL7Gate Drive Control Register 7Section 7.2.11
29hCSA_CTRLCSA Control RegisterSection 7.2.12
2BhMON_CTRL1Monitor Control Register 1Section 7.2.13
2ChMON_CTRL2Monitor Control Register 2Section 7.2.14
2DhMON_CTRL3Monitor Control Register 3Section 7.2.15
2EhMON_CTRL4Monitor Control Register 4Section 7.2.16
36hSPI_TESTSPI Test RegisterSection 7.2.17
48hOTP_USROTP User controlSection 7.2.18

Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for access types in this section.

Table 7-10 CONTROL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.2.1 IC_CTRL1 Register (Address = 1Ah) [Reset = 0000h]

IC_CTRL1 is shown in Table 7-11.

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Table 7-11 IC_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0b Reserved
0VDDSDO_SELR/W0b VDDSDO regulator output selection bit. The bit determines VOH level of SDO and PHCx between 3.3V mode or 5V mode. The VIH/VIL of input buffers are not affected by VDDSDO_SEL bit. Before VDDSDO_SEL is set, VDDSDO_MON_LVL needs to be correctly configured.
  • 0b = SDO/PHCx 3.3V mode
  • 1b = SDO/PHCx 5V mode

7.2.2 IC_CTRL2 Register (Address = 1Bh) [Reset = 0006h]

IC_CTRL2 is shown in Table 7-12.

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Table 7-12 IC_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
15ENABLE_DRVR/W0b Enable predriver bit. The bit is cleared to 0b if one or multiple predriver shutdown conditions are detected and fault flags are set to 1b and if ALL_CH is 1b, or if DRVOFF is driven high. The ENABLE_DRV bit is forced to 0b by device while the fault condition exists or while DRVOFF is high. At power up, write access to ENABLE_DRV is ignored and the bit cannot be set to 1 until nFAULT goes high. After nFAULT goes high, wait 5us and set ENABLE_DRV to 1b. During initial setup, it's recommended to set the gate drive current IDRVx settings before ENABLE_DRV is set to 1b.
  • 0b = INHx and INLx digital inputs are ignored and the gate driver outputs are pulled low (active pull down) by default.
  • 1b = Gate driver outputs are controlled by INHx and INL digital inputs. If IDRVP or IDRVN register values is modified while ENABLE_DRV is 1b, the one PWM cycle delay is expected to get the gate driver current updated.
14MODE_NSLEEPR/W0b nSLEEP Mode.
  • 0b = nSLEEP is active low and device enters sleep mode when nSLEEP is driven low.
  • 1b = nSLEEP is active low and device enters DRVOFF shutdown mode when nSLEEP is driven low. Internal regulators including GVDD charge pump and TCP/VCP charge pumps are active. If WDT_FLT is detected, the device enters sleep mode when nSLEEP is low regardless of MODE_NSLEEP bit.
13CFG_CRC_ENR/W0b Enable configuration data CRC function
  • 0b = Configuration DATA CRC function is disabled.
  • 1b = Configuration Data CRC function is enabled.
12CLKMON_ENR/W0b Clock monitor enable
  • 0b = Clock monitor is disabled.
  • 1b = Clock monitor is enabled.
11CSA_ENR/W0b Current Sense Amplifier Enable. If GVDD_UV_MODE is 0b (Warning mode), MCU must maintain GVDD_UV flag is 0b before CSA_EN bit is set to 1b. If GVDD_UV_MODE is 1b (Fault mode), IC disables CSA amplifier when GVDD_UV is detected.
  • 0b = CSA is disabled. SOx are HiZ state.
  • 1b = CSA is enabled.
10CSA_AZ_DISR/W0b Current Sense Amplifier Auto Zero function disable
  • 0b = CSA Auto Zero function is enabled. This bit is 0b during normal PWM/CSA operation.
  • 1b = CSA Auto Zero function is disabled. The purpose of this bit is to disable switching activity of current sense amplifier for auto zero function. Refer to timing requirements if this bit is used.
9RESERVEDR0b Reserved
8GVDD_MODER/W0b GVDD Charge pump LDO mode control
  • 0b = Normal GVDD operation. Charge pump mode and LDO mode are controlled by device.
  • 1b = LDO mode. GVDD charge pump clock is disabled. (charge pump switching operation is disabled).
7-6VCP_MODER/W00b VCP/TCP mode control
  • 00b = Normal VCP/TCP operation. VCP/TCP is enabled at power up. TCP SW is enabled when SPI ENABLE_DRV is 0. When DRVOFF is high and if system expects the device to keep BST cap stay charged, VCP_MODE must be 00b.
  • 01b = VCP/CPTH-SHx switch is disabled. VCP/TCP charge pump clock is active. This bit is valid regardless of SPI ENABLE_DRV.
  • 10b = VCP/TCP shutdown. Both VCP/CPTH-SHx switch and VCP/TCP charge pump clock are disabled. This bit is valid regardless of SPI ENABLE_DRV.
  • 11b = Normal VCP/TCP operation. VCP/TCP is enabled at power up. TCP SW is disabled when SPI ENABLE_DRV is 0.
5-4RESERVEDR0b Reserved
3-1LOCKR/W011b Lock and unlock the register setting
Bit settings not listed have no effect.
  • 011b = Unlock all the registers
  • 110b = Lock the settings by ignoring further register writes except to these bits.
0CLR_FLTR/W0b Clear fault. After fault event is detected and fault flag is set, TI recommends to issue CLR_FLT command first, then ENABLE_DRV command next in a separate SPI frame. If CLR_FLT and ENABLE_DRV commands are issued in the same SPI frame, CLR_FLT is higher priority and ENABLE_DRV is not set if the fault flag is already latched and the device is waiting CLR_FLT.
  • 0b = No action
  • 1b = Clear faults. Self-clear to 0b.

7.2.3 IC_CTRL3 Register (Address = 1Ch) [Reset = 8009h]

IC_CTRL3 is shown in Table 7-13.

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Table 7-13 IC_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
15SPI_CRC_ENR/W1b SPI CRC Enable
  • 0b = SPI CRC is disabled. One SPI frame is 8-bit command, 16-bit data.
  • 1b = SPI CRC is enabled. One SPI frame is 8-bit command, 16-bit data, and 8-bit CRC.
14WARN_MODER/W0b Warning nFAULT mode; Control nFAULT response for warning events
  • 0b = No nFAULT reporting for warning response. Status flags are set.
  • 1b = nFAULT is driven low for warning response. Status flags are set.
13RESERVEDR0b Reserved
12DIS_SSCR/W0b TI Internal design parameter: No change is required unless notified by TI. The bit disables Spread Spectrum Clocking feature of the device internal oscillator
  • 0b = Normal operation. Spread Spectrum Clocking feature is enabled.
  • 1b = Spread Spectrum Clock feature is disabled for TI debug purpose.
11RESERVEDR0b Reserved
10TCP_EN_DLYR/W0b Delay time to activate trickle charge pump after the device detects PWM inactive (INHx=INLx=Low)
  • 0b = 100us (typ)
  • 1b = 250us (typ)
9DRVOFF_PDSEL_HSR/W0b DROVFF Pull-down select for high-side gate driver
  • 0b = High-side gate driver outputs GHx are semi active pull-down (RPDSA_HS) if DRVOFF is high.
  • 1b = High-side gate driver outputs GHx are passive pull-down (RPD_HS) if DRVOFF is high.
8DRVOFF_PDSEL_LSR/W0b DROVFF Pull-down select for low-side gate driver
  • 0b = Low-side gate driver outputs GLx are semi active pull-down (RPDSA_LS) if DRVOFF is high.
  • 1b = Low-side gate driver outputs GLx are passive pull-down (RPD_LS) if DRVOFF is high.
7-4RESERVEDR0b Reserved
3OT_LVLR/W1b Overtemperature shutdown threshold selection
  • 0b = Grade 1 mode
  • 1b = Grade 0 mode
2RESERVEDR0b Reserved
1-0OTSD_MODER/W01b Overtemperature shutdown mode
  • 00b = Warning mode
  • 01b = Fault (shutdown) mode
  • 10b = No report. No shutdown.
  • 11b = No report. No shutdown

7.2.4 GD_CTRL1 Register (Address = 1Eh) [Reset = 0138h]

GD_CTRL1 is shown in Table 7-14.

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Table 7-14 GD_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0b Reserved
14-12PWM_MODER/W000b PWM mode.
  • 000b = 6x PWM mode (INHx/INLx)
  • 001b = 3x PWM mode with INLx enable control
  • 010b = 3x PWM mode with SPI enable control (DRVEN_x). INLx don't affect PWM control. MCU must use this mode to generate PWM if PHC_OUTEN is 1b.
  • 011b = 1x PWM mode (INHx/INLx)
  • 100b = Reserved.
  • 101b = SPI Gate Drive Mode. DRV_GHx and DRV_GLx register bits are valid.
  • 110b = 6x PWM mode (INHx/INLx)
  • 111b = 6x PWM mode (INHx/INLx)
11RESERVEDR0b Reserved
10-9SGD_MODER/W00b Smart Gate Drive mode
  • 00b = Smart Gate Drive with fixed peak current control. TDRVN_D is not valid and ignored.
  • 01b = Smart Gate Drive with dynamic peak current control. TDRVN_D is enabled.
8SGD_TMP_ENR/W1b Enable dynamic temperature control of Smart Gate Drive.
  • 0b = SGD temperature control is disabled. IDRVP and IDRVN are constant.
  • 1b = SGD temperature control is enabled. IDRVP (300mA or higher) and IDRVN (600mA or higher) are adjusted based on DIE_TEMP information. The IDRIVx adjustment takes place every 9ms by the device or when the SGD_TMP_EN bit changes from 0b to 1b.
7STP_MODER/W0b Shoot-through protection report mode
Note: Other than PWM_MODE 000b, STP_MODE shall be set to 1b, otherwise a false STP_FLT flag is reported.
  • 0b = Shoot-through protection is enabled. The gate driver outputs are forced low during a shoot-through condition. The SPI fault flag is set and the nFAULT pin is driven low when the condition is detected. Set STP_MODE to 0b only for PWM_MODE 000b (6xPWM mode).
  • 1b = Shoot-through protection is enabled but no reporting is performed. The gate driver outputs are forced low during a shoot-through condition. No SPI fault flag is set, and the nFAULT pin stays high when the condition is detected. Other than PWM_MODE 000b, STP_MODE shall be set to 1b not to report a false STP_FLT flag.
6RESERVEDR0b Reserved
5-3DEADTR/W111b Gate driver dead time
  • 000b = 70ns
  • 001b = 200ns
  • 010b = 300ns
  • 011b = 500ns
  • 100b = 750ns
  • 101b = 1000ns
  • 110b = 1500ns
  • 111b = 2000ns
2DEADT_MODER/W0b Dead Time Insertion Mode.
  • 0b = Dead time is inserted when device input (INHx or INLx) goes low.
  • 1b = Dead time is inserted by monitoring gate driver outputs (GHx or GLx).
1-0DEADT_MODE_6XR/W00b Dead Time Violation Response Mode for 6 PWM mode only. NOTE: Other than 6 PWM mode, dead time is always inserted regardless of the DEADT_MODE bit and no fault is reported to the MCU.
  • 00b = Dead-time protection is enabled. The gate driver control signals are enforced low during the dead time period. The SPI fault flag is set and the nFAULT pin is driven low when the dead time condition is detected.
  • 01b = Dead-time protection is enabled but no reporting is performed. The gate driver outputs are forced low during the dead time period. The SPI fault flag is never set and the nFAULT pin stays high when the dead time condition is detected
  • 10b = Dead-time protection is disabled. No dead time is inserted. No SPI fault flag is set and the nFAULT1 pin stays high. This is applied to both the cases when DEADT_MODE is 0b (monitoring INH or INL) and 1b (monitoring GHx or GLx).
  • 11b = Dead-time protection is enabled and SPI fault is set but no nFAULT reporting is performed. The gate driver outputs are forced low during the dead time period. The nFAULT pin stays high when the dead time condition is detected.

7.2.5 GD_CTRL2 Register (Address = 1Fh) [Reset = 0717h]

GD_CTRL2 is shown in Table 7-15.

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Table 7-15 GD_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0b Reserved
11-8TDRVPR/W0111b Peak source pull up drive timing
  • 0000b = 0.143us
  • 0001b = 0.179us
  • 0010b = 0.321us
  • 0011b = 0.464us
  • 0100b = 0.607us
  • 0101b = 0.750us
  • 0110b = 0.893us
  • 0111b = 1.036us
  • 1000b = 1.321us
  • 1001b = 1.607us
  • 1010b = 1.893us
  • 1011b = 2.179us
  • 1100b = 2.536us
  • 1101b = 2.964us
  • 1110b = 3.393us
  • 1111b = 3.821us
7-4TDRVN_DR/W0001b Peak sink pull down pre-discharge timing
  • 0000b = 70ns
  • 0001b = 140ns
  • 0010b = 211ns
  • 0011b = 281ns
  • 0100b = 351ns
  • 0101b = 421ns
  • 0110b = 491ns
  • 0111b = 561ns
  • 1000b = 632ns
  • 1001b = 702ns
  • 1010b = 772ns
  • 1011b = 842ns
  • 1100b = 912ns
  • 1101b = 982ns
  • 1110b = 1053ns
  • 1111b = 1123ns
3-0TDRVNR/W0111b Peak sink pull down drive timing. Refer to TDRVP

7.2.6 GD_CTRL3 Register (Address = 21h) [Reset = 0700h]

GD_CTRL3 is shown in Table 7-16.

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Table 7-16 GD_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0b Reserved
11-8TDRVN_SDDR/W0111b Smart shutdown discharge timing. Refer to TDRVN_D
7-6RESERVEDR0b Reserved
5-0IDRVN_SDR/W000000b Smart shutdown drive current.

7.2.7 GD_CTRL3B Register (Address = 22h) [Reset = 0000h]

GD_CTRL3B is shown in Table 7-17.

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Table 7-17 GD_CTRL3B Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0b Reserved
13-8IDRVN_D_HR/W000000b Peak sink pull down pre-discharge current for high-side gate driver. Refer to IDRIVE description
7-6RESERVEDR0b Reserved
5-0IDRVN_D_LR/W000000b Peak sink pull down pre-discharge current for low-side gate driver. Refer to IDRIVE description

7.2.8 GD_CTRL4 Register (Address = 23h) [Reset = 0000h]

GD_CTRL4 is shown in Table 7-18.

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Table 7-18 GD_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
15PWM1X_COMR/W0b 1x PWM Commutation Control
  • 0b = 1x PWM mode uses synchronous rectification
  • 1b = 1x PWM mode uses asynchronous rectification
14PWM1X_DIRR/W0b 1x PWM Direction. In 1x PWM mode this bit is ORed with the INHC (DIR) input
13-12PWM1X_BRAKER/W00b 1x PWM output configuration
  • 00b = Outputs follow commanded inputs
  • 01b = Turn on all three low-side MOSFETs
  • 10b = Turn on all three high-side MOSFETs
  • 11b = Turn off all six MOSFETs (coast)
11-10RESERVEDR0b Reserved
9IDRVP_CFGR/W0b IDRVP configuration mode
  • 0b = IDRVP register is not valid and ignored. IDRV_RATIO is used to determine IDRVP parameter if IDRVN is in the range of 000000b (0.7mA) - 100011b (247mA). If IDRVN is 100100b (600mA) - 101100b (2000mA), IDRVP uses the same setting as IDRVN. For example, if IDRVN is set to 100100b (600mA), IDRVP is 100100b (300mA) where pull-up current is typically half of pull-down current.
  • 1b = IDRVP register is used to determine IDRVP parameter. IDRV_RATIO is not valid and is ignored.
8IHOLD_SELR/W0b Select IHOLD pull-up and pull-down current. IHOLD_SEL bit must be configured while PWM is inactive (ENABLE_DRV is 0b).
  • 0b = IHOLD pull-up/down 500mA/1000mA (typ)
  • 1b = IHOLD pull-up/down 260mA/260mA (typ)
7-6RESERVEDR0b Reserved
5DRV_GHAR/W0b Drive GHA by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GHA is driven low
  • 1b = GHA is driven high
4DRV_GHBR/W0b Drive GHB by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GHB is driven low
  • 1b = GHB is driven high
3DRV_GHCR/W0b Drive GHC by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GHC is driven low
  • 1b = GHC is driven high
2DRV_GLAR/W0b Drive GLA by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GLA is driven low
  • 1b = GLA is driven high
1DRV_GLBR/W0b Drive GLB by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GLB is driven low
  • 1b = GLB is driven high
0DRV_GLCR/W0b Drive GLC by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GLC is driven low
  • 1b = GLC is driven high

7.2.9 GD_CTRL5 Register (Address = 24h) [Reset = 0007h]

GD_CTRL5 is shown in Table 7-19.

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Table 7-19 GD_CTRL5 Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR0b Reserved
2DRVEN_AR/W1b DRVEN_A = 0 enforces GHA and GLA low with active pull down without shutdown sequence. This bit is valid for any PWM_MODE settings. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GHA and GLA are actively pulled down (low). ENABLE_DRV is not affected by this bit.
  • 1b = No affect. GHA and GLA are controlled normally depending following PWM_MODE setting.
1DRVEN_BR/W1b DRVEN_B = 0 enforces GHB and GLB low with active pull down without shutdown sequence. This bit is valid for any PWM_MODE settings. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GHB and GLB are actively pulled down (low). ENABLE_DRV is not affected by this bit.
  • 1b = No affect. GHB and GLB are controlled normally depending following PWM_MODE setting.
0DRVEN_CR/W1b DRVEN_C = 0 enforces GHC and GLC low with active pull down without shutdown sequence. This bit is valid for any PWM_MODE settings. This bit is valid when ENABLE_DRV is 1b.
  • 0b = GHC and GLC are actively pulled down (low). ENABLE_DRV is not affected by this bit.
  • 1b = No affect. GHC and GLC are controlled normally depending following PWM_MODE setting.

7.2.10 GD_CTRL6 Register (Address = 25h) [Reset = 0000h]

GD_CTRL6 is shown in Table 7-20.

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Table 7-20 GD_CTRL6 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0b Reserved
13-8IDRVP_HR/W000000b High-side peak source pull up current. IDRVP_H is valid if IDRVP_CFG = 1b. IDRVP_H is not valid and ignored if IDRVP_CFG = 0b.
7-6RESERVEDR0b Reserved
5-0IDRVP_LR/W000000b Low-side peak source pull up current. IDRVP_L is valid if IDRVP_CFG = 1b. IDRVP_H is not valid and ignored if IDRVP_CFG = 0b.

7.2.11 GD_CTRL7 Register (Address = 26h) [Reset = 0000h]

GD_CTRL7 is shown in Table 7-21.

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Table 7-21 GD_CTRL7 Register Field Descriptions
BitFieldTypeResetDescription
15-14IDRV_RATIO_HR/W00b High-side IDRVP and IDRVN ratio. IDRV_RATIO_H is valid if IDRVP_CFG = 0b and if the range of IDRVN_H is from 00000b (0.7mA) to 100011b (typ 247mA). IDRIVE_RATIO_H doesn't affect gate driver performance if IDRVN_H is 100100b(600mA) or higher setting. If IDRVP_CFG = 1b, IDRV_RATIO_H is not valid and ignored.
  • 00b = IDRVP is IDRVN x 1
  • 01b = IDRVP is IDRVN x 0.75
  • 10b = IDRVP is IDRVN x 0.5
  • 11b = IDRVP is IDRVN x 0.25
13-8IDRVN_HR/W000000b High-side peak sink pull down current. Refer to Electrical Characteristics table, IDRVN parameter.
7-6IDRV_RATIO_LR/W00b Low-side IDRVP and IDRVN ratio. IDRV_RATIO_L is valid if IDRVP_CFG = 0b and if the range of IDRVN_H is from 00000b (0.7mA) to 100011b (typ 247mA). IDRIVE_RATIO_L doesn't affect gate driver performance if IDRVN_H is 100100b(600mA) or higher setting. If IDRVP_CFG = 1b, IDRV_RATIO_L is not valid and ignored.
  • 00b = IDRVP is IDRVN x 1
  • 01b = IDRVP is IDRVN x 0.75
  • 10b = IDRVP is IDRVN x 0.5
  • 11b = IDRVP is IDRVN x 0.25
5-0IDRVN_LR/W000000b Low-side peak sink pull down current. Refer to Electrical Characteristics table, IDRVN parameter.

7.2.12 CSA_CTRL Register (Address = 29h) [Reset = 0000h]

CSA_CTRL is shown in Table 7-22.

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Table 7-22 CSA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15AREF_DIVR/W0b VREF dividing ratio
  • 0b = 1/2
  • 1b = 1/8
14-12RESERVEDR0b Reserved
11-8CSA_GAIN_AR/W0000b CSA Gain of SOA. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40.
  • 0000b = 5
  • 0001b = 10
  • 0010b = 12
  • 0011b = 16
  • 0100b = 20
  • 0101b = 23
  • 0110b = 25
  • 0111b = 30
  • 1000b = 40
7-4CSA_GAIN_BR/W0000b CSA Gain of SOB. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40.
  • 0000b = 5
  • 0001b = 10
  • 0010b = 12
  • 0011b = 16
  • 0100b = 20
  • 0101b = 23
  • 0110b = 25
  • 0111b = 30
  • 1000b = 40
3-0CSA_GAIN_CR/W0000b CSA Gain of SOC. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40.
  • 0000b = 5
  • 0001b = 10
  • 0010b = 12
  • 0011b = 16
  • 0100b = 20
  • 0101b = 23
  • 0110b = 25
  • 0111b = 30
  • 1000b = 40

7.2.13 MON_CTRL1 Register (Address = 2Bh) [Reset = 4002h]

MON_CTRL1 is shown in Table 7-23.

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Table 7-23 MON_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-14VDRAIN_OV_LVLR/W01b VDRAIN Overvoltage threshold level
  • 00b = 29.5V (typ)
  • 01b = 34.5V (typ)
  • 10b = 53.5V (typ)
  • 11b = 53.5V (typ)
13VDRAIN_MON_MODER/W0b VDRAIN monitor mode for under and over voltage monitors
  • 0b = Warning mode
  • 1b = Fault mode
12BST_OV_MODER/W0b BST pin overvoltage monitor mode
  • 0b = Warning mode
  • 1b = Fault mode
11BST_UV_LATCHR/W0b BST pin undervoltage latch mode
  • 0b = BST_UV is real time monitor. BST_UV is cleared to 0b when VBST exceeds VBST_UV threshold. BST_UV_MODE is ignored.
  • 1b = BST_UV is latched when under voltage condition is detected.
10BST_UV_MODER/W0b BST pin monitor mode. If BST_UV_LATCH is 1b, BST_UV_MODE determines Warning mode or Fault mode. Refer to BST_UV_LATCH register bit.
  • 0b = Warning mode
  • 1b = Fault mode
9BST_UV_LVLR/W0b BST pin undervoltage threshold level VBST_UV
  • 0b = 4.2V (typ)
  • 1b = 7.2V (typ)
8DVDD_OV_MODER/W0b DVDD monitor mode of over voltage monitor
  • 0b = Warning mode
  • 1b = Fault mode
7GVDD_OV_MODER/W0b GVDD monitor mode of over voltage monitor
  • 0b = Warning mode
  • 1b = Fault mode
6GVDD_UV_MODER/W0b GVDD monitor mode of under voltage monitor
  • 0b = Warning mode
  • 1b = Fault mode
5VCP_OV_MODER/W0b VCP monitor mode of over voltage monitor
  • 0b = Warning mode
  • 1b = Fault mode
4VCP_UV_MODER/W0b VCP monitor mode of under voltage monitor
  • 0b = Warning mode
  • 1b = Fault mode
3PVDD_UVW_LVLR/W0b PVDD UV Warning threshold level
2-1PVDD_OV_LVLR/W01b PVDD OV threshold level
0PVDD_OV_MODER/W0b PVDD OV threshold monitor mode
  • 0b = Warning mode
  • 1b = Fault mode

7.2.14 MON_CTRL2 Register (Address = 2Ch) [Reset = 1101h]

MON_CTRL2 is shown in Table 7-24.

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Table 7-24 MON_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
15-14VDS_MODER/W00b VDS overcurrent mode
  • 00b = Warning mode.
  • 01b = Fault mode.
  • 10b = Reserved
  • 11b = No report. No shutdown.
13-11VDS_BLKR/W010b VDS overcurrent blanking time
10-8VDS_DEGR/W001b VDS overcurrent deglitch time
7-6VGS_MODER/W00b VGS monitor mode
  • 00b = Warning mode.
  • 01b = Fault mode.
  • 10b = Reserved
  • 11b = No report. No shutdown.
5-3VGS_BLKR/W000b VGS monitor blanking time
2-0VGS_DEGR/W001b VGS monitor deglitch time

7.2.15 MON_CTRL3 Register (Address = 2Dh) [Reset = 003Bh]

MON_CTRL3 is shown in Table 7-25.

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Table 7-25 MON_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0b Reserved
8VGS_LVLR/W0b Gate voltage monitor threshold level when INLx/INHx = High. VGS_LVL_H
  • 0b = 5.7V (typ)
  • 1b = 7.7V (typ)
7-6SNS_OCP_MODER/W00b Monitor mode of VSENSE overcurrent protection (Rshunt monitor)
  • 00b = Warning mode.
  • 01b = Fault mode.
  • 10b = Reserved
  • 11b = No report. No shutdown.
5-3SNS_OCP_LVLR/W111b Threshold voltage of VSENSE overcurrent protection (Rshunt monitor)
  • 000b = 50mV (typ)
  • 001b = 75mV (typ)
  • 010b = 100mV (typ)
  • 011b = 125mV (typ)
  • 100b = 150mV (typ)
  • 101b = 200mV (typ)
  • 110b = 300mV (typ)
  • 111b = 500mV (typ)
2RESERVEDR0b Reserved
1-0SNS_OCP_DEGR/W11b Deglitch time of VSENSE overcurrent protection (Rshunt monitor)
  • 00b = 2.0us (typ)
  • 01b = 4.0us (typ)
  • 10b = 6.0us (typ)
  • 11b = 10.0us (typ)

7.2.16 MON_CTRL4 Register (Address = 2Eh) [Reset = 0000h]

MON_CTRL4 is shown in Table 7-26.

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Table 7-26 MON_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR0b Reserved
5WDT_FLT_MODER/W0b Watchdog Time Fault Mode
  • 0b = Report on nFAULT. No gate driver shutdown.
  • 1b = Report on nFAULT. Gate Driver shutdown.
4WDT_CNTR/W0b Watchdog Time Fault Count
  • 0b = One time WDT fault reports status flag and asserts nFAULT1 pin low.
  • 1b = Three consecutive faults report status flag and assert nFAULT pin low. Internal counter is cleared to 0 after the three consecutive faults are detected. Internal counter can also be cleared if WDT_EN is cleared to 0b.
3WDT_MODER/W0b Watchdog Time MODE
  • 0b = Any valid read access reset the watchdog timer
  • 1b = A valid write access to SPI_TEST resets the watchdog timer
2-1WDT_WR/W00b Watchdog Timer window tWDL (lower window) and tWDU (upper window)
  • 00b = tWDL 0.5ms tWDU 10ms
  • 01b = tWDL 1ms tWDU 20ms
  • 10b = tWDL 2ms tWDU 40ms
  • 11b = tWDL 2ms tWDU 40ms
0WDT_ENR/W0b Watchdog Time Enable
  • 0b = Watchdog timer disabled
  • 1b = Watchdog timer enabled

7.2.17 SPI_TEST Register (Address = 36h) [Reset = 0000h]

SPI_TEST is shown in Table 7-27.

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Table 7-27 SPI_TEST Register Field Descriptions
BitFieldTypeResetDescription
15-0SPI_TESTR/W0000000000000000b SPI Test register. Write access to this register has no effect on device operation.

7.2.18 OTP_USR Register (Address = 48h) [Reset = 0000h]

OTP_USR is shown in Table 7-28.

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Table 7-28 OTP_USR Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0b Reserved
4OTP_USR_P_VERR/W0b Enables memory verification of User OTP Program. The bit is used after user OTP is programmed by user. MCU waits until the bit is cleared to 0 by the device, and then MCU must check OTP_USR_CRC_FLT for the verification result. OTP_USR_PRG and OTP_USR_P_VER shall never be set to 1b at the same time.
  • 0b = User OTP Verification is inactive
  • 1b = User OTP Verification is enabled and is active. The device runs CRC automatically, and OTP_USR_CRC_FLT status bit is set to 1b if User OTP Verification is failing.
3-1OTP_USR_P_ACCR/W000b Access control of User OTP Program and User OTP Verification. The write access of OTP_USR_PRG bit is not available unless the following value is written in sequence; 0x2, 0x1, 0x4. Any other undefined values are ignored and the reset the internal sequence logic. The device returns read 0x7 if the sequence values are accepted. After the sequence is accepted by device (read =0x7), any write access (including 0x2, 0x1, 0x4) to this register resets the sequence logic (read = 0x0).
  • 000b = Read returned data if sequence logic is reset.
  • 001b = The 2nd data to be entered in the sequence
  • 010b = The 1st data to be entered in the sequence
  • 100b = The 3rd data to be entered in the sequence
  • 111b = Read returned data if the sequence commands are accepted by device and write access to OTP_USR_PRG is allowed.
0OTP_USR_PRGW0b Program User OTP. MCU sets the bit to 1 to enable OTP program. MCU waits until the bit is cleared to 0 by the device. OTP_USR_PRG and OTP_USR_P_VER shall never be set to 1b at the same time. When OTP_USR_PRG is set to 1, the following SPI register bits shall be configured accordingly; ENABLE_DRV=0, ADC_EN=0, ADC_EN2=0, PWSPI_EN=0, WDT_EN=0, VCP_MODE=11, CLKMON_EN=0, DRVEN_A=0, DRVEN_B=0, DRVEN_C=0, CSA_EN=0, GVDD_MODE=1.
  • 0b = User OTP Program is inactive.
  • 1b = User OTP Program is enabled and is active.