SLVSHC8 May   2023 DRV8334-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions 48-Pin DRV8334-Q1
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 3x PWM Mode with SPI enable control
          4. 6.3.1.1.4 1x PWM Mode
          5. 6.3.1.1.5 SPI Gate Drive Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 GVDD Charge pump/LDO
          3. 6.3.1.2.3 VCP Trickle Charge pump
          4. 6.3.1.2.4 Gate Driver Output
          5. 6.3.1.2.5 Passive and Semi-active pull-down resistor
          6. 6.3.1.2.6 TDRIVE Gate Drive Timing Control
          7. 6.3.1.2.7 Propagation Delay
          8. 6.3.1.2.8 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 Low-Side Current Sense Amplifiers
        1. 6.3.2.1 Unidirectional Current Sense Operation
        2. 6.3.2.2 Bidirectional Current Sense Operation
      3. 6.3.3 Gate Driver Shutdown
        1. 6.3.3.1 DRVOFF Gate Driver Shutdown
        2. 6.3.3.2 Gate Driver Shutdown Timing Sequence
      4. 6.3.4 Gate Driver Protective Circuits
        1. 6.3.4.1  PVDD Supply Undervoltage Warning (PVDD_UVW)
        2. 6.3.4.2  PVDD Supply Undervoltage Lockout (PVDD_UV)
        3. 6.3.4.3  PVDD Supply Overvoltage Fault (PVDD_OV)
        4. 6.3.4.4  GVDD Undervoltage Lockout (GVDD_UV)
        5. 6.3.4.5  GVDD Overvoltage Fault (GVDD_OV)
        6. 6.3.4.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.4.7  BST Overvoltage Fault (BST_OV)
        8. 6.3.4.8  VCP Undervoltage Fault (CP_OV)
        9. 6.3.4.9  VCP Overvoltage Fault (CP_OV)
        10. 6.3.4.10 VDRAIN Undervoltage Fault (VDRAIN_UV)
        11. 6.3.4.11 VDRAIN Overvoltage Fault (VDRAIN_OV)
        12. 6.3.4.12 MOSFET VGS Monitoring Protection
        13. 6.3.4.13 MOSFET VDS Overcurrent Protection (VDS_OCP)
        14. 6.3.4.14 VSENSE Overcurrent Protection (SEN_OCP)
        15. 6.3.4.15 Phase Comparators
        16. 6.3.4.16 Thermal Shutdown (OTSD)
        17. 6.3.4.17 Thermal Warning (OTW)
        18. 6.3.4.18 OTP CRC
        19. 6.3.4.19 SPI Watchdog Timer
        20. 6.3.4.20 Phase Diagnostic
    4. 6.4 Device Functional Modes
      1. 6.4.1 Gate Driver Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Operating Mode
      2. 6.4.2 Device Power Up Sequence
    5. 6.5 Programming
      1. 6.5.1 SPI
      2. 6.5.2 SPI Format
      3. 6.5.3 SPI Format Diagrams
  8. 7 Register Maps
    1. 7.1 STATUS Registers
    2. 7.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
      2. 8.2.2 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1 STATUS Registers

Table 7-1 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 STATUS Registers
AddressAcronymRegister NameSection
0hIC_STAT1IC Status Register 1Section 7.1.1
1hIC_STAT2IC Status Register 2Section 7.1.2
2hIC_STAT3IC Status Register 3Section 7.1.3
3hIC_STAT4IC Status Register 4Section 7.1.4
4hIC_STAT5IC Status Register 5Section 7.1.5
5hIC_STAT6IC Status Register 6Section 7.1.6

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 STATUS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

7.1.1 IC_STAT1 Register (Address = 0h) [Reset = 8000h]

IC_STAT1 is shown in Table 7-3.

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Table 7-3 IC_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
15SPI_OKR1b No SPI Fault is detected
  • 0b = SPI Fault is detected
  • 1b = No fault
14FAULTR0b Logic OR of FAULT status registers. Mirrors nFAULT pin.
  • 0b = nFAULT status logic-low
  • 1b = nFAULT status logic-high. One or multiple fault events detected.
13WARNR0b Logic OR of WARN status, except OTW
  • 0b = No warning event detected
  • 1b = One or multiple warning event detected
12VDSR0b Logic OR of VDS overcurrent detection
  • 0b = No VDS events detected.
  • 1b = One or multiple VDS events detected.
11VGSR0b Logic OR of VGS detection
  • 0b = No VGS events detected.
  • 1b = One or multiple VGS events detected.
10SNS_OCPR0b Logic OR of Sense overcurrent detection
  • 0b = No sense overcurrent events detected.
  • 1b = One or multiple sense overcurrent events detected.
9OVR0b Logic OR of supply voltage overvoltage detection
  • 0b = No overvoltage events detected.
  • 1b = One or more overvoltage events detected.
8UVR0b Logic OR of supply voltage undervoltage detection
  • 0b = No undervoltage events detected.
  • 1b = One or more undervoltage events detected.
7-2RESERVEDR0b Reserved
1OTWR0b Overtemperature Warning Status Bit
  • 0b = No event is detected
  • 1b = Overtemperature warning event detected
0DRV_STATR0b Indicates Driver Enable Status. Mirrors ENABLE_DRV register bit

7.1.2 IC_STAT2 Register (Address = 1h) [Reset = 0000h]

IC_STAT2 is shown in Table 7-4.

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Table 7-4 IC_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
15CBC_STR0b VDS and SNS_OCP monitor Cycle By Cycle (CBC) counter activity status. If CBC is enabled (CBC is 1b), CBC counter is incremented when VDS or SNS_OCP condition is detected. CBC_ST is 1 if CBC counter is not 0 (CBC counter > 0) to indicate one or multiple VDS or SNS_OCP conditions have been detected.
  • 0b = CBC counter is 0
  • 1b = CBC counter is not 0 if CBC is enabled.
14-11RESERVEDR0b Reserved
10SNS_OCP_AR0b Overcurrent on External Sense Resistor Status Bit on phase A
9SNS_OCP_BR0b Overcurrent on External Sense Resistor Status Bit on phase B
8SNS_OCP_CR0b Overcurrent on External Sense Resistor Status Bit on phase C
7-6RESERVEDR0b Reserved
5VDS_HAR0b VDS Overcurrent Status on the A High-side MOSFET
4VDS_LAR0b VDS Overcurrent Status on the A Low-side MOSFET
3VDS_HBR0b VDS Overcurrent Status on the B High-side MOSFET
2VDS_LBR0b VDS Overcurrent Status on the B Low-side MOSFET
1VDS_HCR0b VDS Overcurrent Status on the C High-side MOSFET
0VDS_LCR0b VDS Overcurrent Status on the C Low-side MOSFET

7.1.3 IC_STAT3 Register (Address = 2h) [Reset = 0000h]

IC_STAT3 is shown in Table 7-5.

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Table 7-5 IC_STAT3 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR0b Reserved
5VGS_HAR0b Gate driver fault status on the A High-side MOSFET.
4VGS_LAR0b Gate driver fault status on the A Low-side MOSFET.
3VGS_HBR0b Gate driver fault status on the B High-side MOSFET.
2VGS_LBR0b Gate driver fault status on the B Low-side MOSFET.
1VGS_HCR0b Gate driver fault status on the C High-side MOSFET.
0VGS_LCR0b Gate driver fault status on the C Low-side MOSFET.

7.1.4 IC_STAT4 Register (Address = 3h) [Reset = 0000h]

IC_STAT4 is shown in Table 7-6.

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Table 7-6 IC_STAT4 Register Field Descriptions
BitFieldTypeResetDescription
15PVDD_OVR0b PVDD overvoltage status
14PVDD_UVR0b PVDD undervoltage status
13VDRAIN_OVR0b VDRAIN overvoltage status
12VDRAIN_UVR0b VDRAIN undervoltage status
11VCP_OVR0b VCP overvoltage status
10VCP_UVR0b VCP undervoltage status
9GVDD_OVR0b GVDD overvoltage status
8GVDD_UVR0b GVDD undervoltage status
7RESERVEDR0b Reserved
6RESERVEDR0b Reserved
5BSTA_OVR0b BST overvoltage on the A High-side MOSFET
4BSTA_UVR0b BST undervoltage on the A High-side MOSFET
3BSTB_OVR0b BST overvoltage on the B High-side MOSFET
2BSTB_UVR0b BST undervoltage on the B High-side MOSFET
1BSTC_OVR0b BST overvoltage on the C High-side MOSFET
0BSTC_UVR0b BST undervoltage on the C High-side MOSFET

7.1.5 IC_STAT5 Register (Address = 4h) [Reset = 0000h]

IC_STAT5 is shown in Table 7-7.

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Table 7-7 IC_STAT5 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0b Reserved
14PVDD_UVWR0b PVDD undervoltage warning status
13-11RESERVEDR0b Reserved
10GVDD_CP_LDOR0b GVDD operating mode status
  • 0b = Charge pump
  • 1b = LDO mode
9OTSDR0b
8WDT_FLTR0b Watch dog timer fault bit
7SPI_CRC_FLTR0b SPI CRC fault bit
6SPI_ADDR_FLTR0b SPI Address fault bit
5SPI_CLK_FLTR0b SPI Clock Framing fault bit. For 32-bit frame (SPI_CRC_EN is 1), the SPI_CLK_FLT is set to 1 if the number of SPI clock of one SPI frame is 1 to 31, 33 or higher. The SPI_CLK_FLT is 0 if the number of SPI clocks is 0 or 32. For 24-bit frame (SPI_CRC_EN is 0b), the SPI_CLK_FLT is 0 if the number of SPI clocks is 0 or 24. For 96-bit frame, the SPI_CLK_FLT is 0 if the number of SPI clocks is 0 or 96. Otherwise, SPI_CLK_FLT is set to 1.
4OTP_CRC_FLTR0b OTP CRC fault bit. A fault of OTP memory used for device production has been detected.
3OTP_USR_CRC_FLTR0b USER OTP CRC fault. A fault of OTP memory used for user configuration has been detected. The OTP_USR_CRC_FLT will always be set to 1b if USER OTP is not used (programmed), and the flag must be cleared at power up. The OTP_USR_CRC_FLT doesn't affect nFAULT or Gate Drivers.
2RESERVEDR0b Reserved
1STP_FLTR0b Shoot Through Protection violation
0DEADT_FLTR0b Dead time violation

7.1.6 IC_STAT6 Register (Address = 5h) [Reset = 0000h]

IC_STAT6 is shown in Table 7-8.

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Table 7-8 IC_STAT6 Register Field Descriptions
BitFieldTypeResetDescription
15PHCA_FLTR0b Indicates phase comparator fault of PHCA
14PHCB_FLTR0b Indicates phase comparator fault of PHCB
13PHCC_FLTR0b Indicates phase comparator fault of PHCC
12RESERVEDR0b Reserved
11VREF_OVR0b VREF input overvoltage status
10VREF_UVR0b VREF input undervoltage status
9VDDSDO_UVR0b Device internal regulator VDDSDO regulator undervoltage status
8RESERVEDR0b Reserved
7DVDD_OVR0b DVDD overvoltage status
6-5RESERVEDR0b Reserved
4ABIST_FLTR0b Analog BIST fault status
3DEV_MODE_FLTR0b Device mode fault status
2-1RESERVEDR0b Reserved
0CLK_MON_FLTR0b Clock monitor fault status