SLVSHD9 Data sheet

SLVSHD9A March 2025 – December 2025 DRV8001-Q1

PRODUCTION DATA

8.2 DRV8000-Q1_CNFG Registers

Table 8-13 lists the memory-mapped registers for the DRV8000-Q1_CNFG registers. All register offset addresses not listed in Table 8-13 should be considered as reserved locations and the register contents should not be modified.

Table 8-13 DRV8000-Q1_CNFG Registers

Offset	Acronym	Register Name	Section
9h	IC_CNFG1	IC configuration register 1.	Section 8.2.1
Ah	IC_CNFG2	IC configuration register 2.	Section 8.2.2
14h	HB_ITRIP_DG	Half-bridge ITRIP deglitch configuration register 2.	Section 8.2.3
15h	HB_OUT_CNFG1	Half-bridge output 5 and 6 configuration register.	Section 8.2.4
16h	HB_OUT_CNFG2	Half-bridge output 1-4 configuration register.	Section 8.2.5
17h	HB_OCP_CNFG	Half-bridge overcurrent deglitch configuration register.	Section 8.2.6
18h	HB_OL_CNFG1	Half-bridge active and passive open-load enable register	Section 8.2.7
19h	HB_OL_CNFG2	Half-bridge active open-load threshold select register.	Section 8.2.8
1Ah	HB_SR_CNFG	Half-bridge slew rate configuration register.	Section 8.2.9
1Bh	HB_ITRIP_CNFG	Half-bridge ITRIP configuration register 1.	Section 8.2.10
1Ch	HB_ITRIP_FREQ	Half-bridge ITRIP frequency configuration register 2.	Section 8.2.11
1Dh	HS_HEAT_OUT_CNFG	High-side and heater driver output configuration register.	Section 8.2.12
1Eh	HS_OC_CNFG	High-side driver overcurrent threshold configuration register.	Section 8.2.13
1Fh	HS_OL_CNFG	High-side driver open load threshold configuration register.	Section 8.2.14
20h	HS_REG_CNFG1	High-side driver regulation configuration register.	Section 8.2.15
21h	HS_REG_CNFG2	High-side driver regulation configuration register.	Section 8.2.16
22h	HS_PWM_FREQ_CNFG	High-side driver PWM generator frequency configuration register.	Section 8.2.17
23h	HEAT_CNFG	Heater configuration register.	Section 8.2.18
24h	EC_CNFG	Electrochrome configuration register.	Section 8.2.19
25h	HS_REG_CNFG3	High-side driver regulation configuration register.	Section 8.2.20
26h	SPARE_CNFG2	Spare configuration	Section 8.2.21
27h	OUT1_HS_MODE_DC	Duty cycle configuration for OUT1.	Section 8.2.22
28h	OUT2_HS_MODE_DC	Duty cycle configuration for OUT2.	Section 8.2.23

Complex bit access types are encoded to fit into small table cells. Table 8-14 shows the codes that are used for access types in this section.

Table 8-14 DRV8000-Q1_CNFG Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.2.1 IC_CNFG1 Register (Offset = 9h) [Reset = 0002h]

IC_CNFG1 is shown in Table 8-15.

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Includes configurations charge pump and watchdog, and fault levels and reactions for supply, charge pump, thermal, and watch dog faults.

Table 8-15 IC_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	OTSD_MODE	R/W	0h	Sets overtemperature shutdown behavior. If any thermal cluster reaches OT, the device shuts down all drivers or affected drivers only (drivers in zone 3, for example). 0b = Global shutdown. 1b = Affected driver shutdown only.
14	RESERVED	R/W	0h	Reserved
13	RSVD	R	0h	Reserved.
12	PVDD_OV_MODE	R/W	0h	PVDD supply overvoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery.
11-10	PVDD_OV_DG	R/W	0h	PVDD supply overvoltage monitor deglitch time. 00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs
9	PVDD_OV_LVL	R/W	0h	PVDD supply overvoltage monitor threshold. 0b = 22 V 1b = 28 V
8	RESERVED	R/W	0h	Reserved
7-6	CP_MODE	R/W	0h	Charge pump operating mode. 00b = Automatic switch between tripler and doubler mode. 01b = Always doubler mode. 10b = Always tripler mode. 11b = RSVD
5	VCP_UV_MODE	R/W	0h	VCP charge pump undervoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery.
4	PVDD_UV_MODE	R/W	0h	PVDD supply undervoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery.
3	WD_EN	R/W	0h	Watchdog timer enable. 0b = Watchdog timer disabled. 1b = Watchdog timer enabled.
2	WD_FLT_M	R/W	0h	Watchdog fault mode. Watchdog fault is cleared by CLR_FLT. 0b = Watchdog fault is reported to WD_FLT and WARN register bits. Drivers remain enabled and FAULT bit is not asserted. 1b = Watchdog fault is reported to WD_FLT and FAULT register bits. All drivers are disabled in response to watchdog fault.
1	WD_WIN	R/W	1h	Watchdog timer window. 0b = 4 to 12 ms 1b = 10 to 100 ms
0	EN_SSC	R/W	0h	Spread spectrum clocking. 0b = Disabled. 1b = Enabled.

8.2.2 IC_CNFG2 Register (Offset = Ah) [Reset = 0000h]

IC_CNFG2 is shown in Table 8-16.

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Includes thermal cluster warning disable bits.

Table 8-16 IC_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	ZONE4_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 4. Enabled = 0b Disabled = 1b
6	ZONE3_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 3. Enabled = 0b Disabled = 1b
5	ZONE2_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 2. Enabled = 0b Disabled = 1b
4	ZONE1_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 1. Enabled = 0b Disabled = 1b
3	ZONE4_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 4. Enabled = 0b Disabled = 1b
2	ZONE3_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 3. Enabled = 0b Disabled = 1b
1	ZONE2_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 2. Enabled = 0b Disabled = 1b
0	ZONE1_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 1. Enabled = 0b Disabled = 1b

8.2.3 HB_ITRIP_DG Register (Offset = 14h) [Reset = 0000h]

HB_ITRIP_DG is shown in Table 8-17.

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Configures ITRIP deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs.

Table 8-17 HB_ITRIP_DG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-10	OUT6_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 6. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
9-8	OUT5_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 5. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
7-6	OUT4_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 4. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
5-4	OUT3_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 3. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
3-2	OUT2_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 2. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
1-0	OUT1_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 1. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs

8.2.4 HB_OUT_CNFG1 Register (Offset = 15h) [Reset = 0000h]

HB_OUT_CNFG1 is shown in Table 8-18.

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Configures the output mode for each half-bridge, sets IPROPI sample and hold circuit, and half-bridge pair freewheeling.

Table 8-18 HB_OUT_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	NSR_OUT6_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 6. Passive freewheeling = 0b Active freewheeling = 1b
13	NSR_OUT5_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 5. Passive freewheeling = 0b Active freewheeling = 1b
12	NSR_OUT4_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 4. Passive freewheeling = 0b Active freewheeling = 1b
11	NSR_OUT3_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridges 3. Passive freewheeling = 0b Active freewheeling = 1b
10	NSR_OUT2_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 2. Passive freewheeling = 0b Active freewheeling = 1b
9	NSR_OUT1_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 1. Passive freewheeling = 0b Active freewheeling = 1b
8	IPROPI_SH_EN	R/W	0h	Enables IPROPI sample and hold circuit.
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5-3	OUT6_CNFG	R/W	0h	Configuration for half-bridge 6. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control
2-0	OUT5_CNFG	R/W	0h	Configuration for half-bridge 5. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control

8.2.5 HB_OUT_CNFG2 Register (Offset = 16h) [Reset = 0000h]

HB_OUT_CNFG2 is shown in Table 8-19.

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Configures the output mode for each half-bridge.

Table 8-19 HB_OUT_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13-11	OUT4_CNFG	R/W	0h	Configuration for half-bridge 4. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control
10-8	OUT3_CNFG	R/W	0h	Configuration for half-bridge 3. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control
7	OUT2_MODE	R/W	0h	Bit to enable OUT2 as High Side driver with internal PWM. OUT2_CNFG used for enabling and disabling the driver PWM settings - Freq: PWM_OUT2_FREQ, DC: OUT2_DC.
6	OUT1_MODE	R/W	0h	Bit to enable OUT1 as High Side driver with internal PWM. OUT1_CNFG used for enabling and disabling the driver PWM settings - Freq: PWM_OUT1_FREQ, DC: OUT1_DC.
5-3	OUT2_CNFG	R/W	0h	Configuration for half-bridge 2. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control
2-0	OUT1_CNFG	R/W	0h	Configuration for half-bridge 1. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control

8.2.6 HB_OCP_CNFG Register (Offset = 17h) [Reset = 0000h]

HB_OCP_CNFG is shown in Table 8-20.

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Overcurrent deglitch for half-bridges configuration register.

Table 8-20 HB_OCP_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-10	OUT6_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 6. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs
9-8	OUT5_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 5. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs
7-6	OUT4_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 4. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs
5-4	OUT3_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 3. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs
3-2	OUT2_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 2. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs
1-0	OUT1_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 1. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs

8.2.7 HB_OL_CNFG1 Register (Offset = 18h) [Reset = 0000h]

HB_OL_CNFG1 is shown in Table 8-21.

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Configures active and off-state open load detection circuits for half-bridges.

Table 8-21 HB_OL_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13-12	HB_OLP_CNFG	R/W	0h	Off-state diagnostics configuration. 00b = Off-state disabled 01b = OUT X Pullup enabled, OUT Y pulldown enabled, OUT Y selected, VREF Low 10b = OUT X Pullup enabled, OUT Y pulldown enabled, OUT X selected, VREF High 11b = OUT X Pulldown enabled, OUT Y pullup enabled, OUT Y selected, VREF Low
11-8	HB_OLP_SEL	R/W	0h	Off-state open load diagnostics enable for half-bridges. 0000b = Disabled 0001b = OUT1 and OUT2 0010b = OUT1 and OUT3 0011b = OUT1 and OUT4 0100b = OUT1 and OUT5 0101b = OUT1 and OUT6 0110b = OUT2 and OUT3 0111b = OUT2 and OUT4 1000b = OUT2 and OUT5 1001b = OUT2 and OUT6 1010b = OUT3 and OUT4 1011b = OUT3 and OUT5 1100b = OUT3 and OUT6 1101b = OUT4 and OUT5 1110b = OUT4 and OUT6 1111b = OUT5 and OUT6
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	OUT6_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 6. 0b = Disabled 1b = Enabled
4	OUT5_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 5. 0b = Disabled 1b = Enabled
3	OUT4_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 4. 0b = Disabled 1b = Enabled
2	OUT3_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 3. 0b = Disabled 1b = Enabled
1	OUT2_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 2. 0b = Disabled 1b = Enabled
0	OUT1_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 1. 0b = Disabled 1b = Enabled

8.2.8 HB_OL_CNFG2 Register (Offset = 19h) [Reset = 0000h]

HB_OL_CNFG2 is shown in Table 8-22.

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Configures cycle count threshold for active open load detection circuits of half-bridges.

Table 8-22 HB_OL_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-10	OUT6_OLA_TH	R/W	0h	Sets the half-bridge 6 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles
9-8	OUT5_OLA_TH	R/W	0h	Sets the half-bridge 5 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles
7-6	OUT4_OLA_TH	R/W	0h	Sets the half-bridge 4 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles
5-4	OUT3_OLA_TH	R/W	0h	Sets the half-bridge 3 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles
3-2	OUT2_OLA_TH	R/W	0h	Sets the half-bridge 2 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles
1-0	OUT1_OLA_TH	R/W	0h	Sets the half-bridge 1 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles

8.2.9 HB_SR_CNFG Register (Offset = 1Ah) [Reset = 0000h]

HB_SR_CNFG is shown in Table 8-23.

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Configures slew rate timing for each half-bridge.

Table 8-23 HB_SR_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-10	OUT6_SR	R/W	0h	Configures slew rate for half-bridge 6. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs
9-8	OUT5_SR	R/W	0h	Configures slew rate for half-bridge 5. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs
7-6	OUT4_SR	R/W	0h	Configures slew rate for half-bridge 4. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs
5-4	OUT3_SR	R/W	0h	Configures slew rate for half-bridge 3. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs
3-2	OUT2_SR	R/W	0h	Configures slew rate for half-bridge 2. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs
1-0	OUT1_SR	R/W	0h	Configures slew rate for half-bridge 1. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs

8.2.10 HB_ITRIP_CNFG Register (Offset = 1Bh) [Reset = 0000h]

HB_ITRIP_CNFG is shown in Table 8-24.

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Configures ITRIP levels and enables ITRIP for each half-bridge. ITRIP levels are shared between half-bridge pairs.

Table 8-24 HB_ITRIP_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	OUT6_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 6.
14	OUT5_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 5.
13	OUT4_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 4.
12	OUT3_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 3.
11	OUT2_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 2.
10	OUT1_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 1.
9-8	OUT6_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold level for half-bridge 6. 00b = 2.3 A. 01b = 5.4 A 10b = 6.2 A 11b = Reserved.
7-6	OUT5_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold level for half-bridge 5. 00b = 2.9 A 01b = 6.6 A 10b = 7.6 A 11b = Reserved.
5-4	OUT4_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold level for half-bridge 4. 00b = 1.3 A 01b = 2.5 A 10b = 3.4 A 11b = Reserved.
3-2	OUT3_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold level for half-bridge 3. 00b = 1.3 A 01b = 2.5 A 10b = 3.4 A 11b = Reserved.
1	OUT2_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold level for half-bridge 2. 0b = 0.7 A 1b = 0.875 A
0	OUT1_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold level for half-bridge 1. 0b = 0.7 A 1b = 0.875 A

8.2.11 HB_ITRIP_FREQ Register (Offset = 1Ch) [Reset = 0000h]

HB_ITRIP_FREQ is shown in Table 8-25.

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Configures ITRIP frequency and deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs.

Table 8-25 HB_ITRIP_FREQ Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13-12	HB_TOFF_SEL	R/W	0h	Toff selection for OUT1-6 half bridge drivers. Here T is decided by OUTx_ITRIP_FREQ. 00b - Zero, disabled 01b - Toff = T/2 10b - Toff=T/4 11b - Toff=T
11-10	OUT6_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 6. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
9-8	OUT5_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 5. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
7-6	OUT4_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 4. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
5-4	OUT3_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 3. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
3-2	OUT2_ITRIP_FREQ/PWM_OUT2_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 2. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz When OUT2_MODE = 1. Used for PWM FREQ settings PWM_OUT2_FREQ: 00b - 108Hz 01b - 217Hz 10b - 289Hz 11b - 434Hz
1-0	OUT1_ITRIP_FREQ/PWM_OUT1_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 1. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz When OUT1_MODE = 1. Used for PWM FREQ settings PWM_OUT1_FREQ: 00b - 108Hz 01b - 217Hz 10b - 289Hz 11b - 434Hz

8.2.12 HS_HEAT_OUT_CNFG Register (Offset = 1Dh) [Reset = 0000h]

HS_HEAT_OUT_CNFG is shown in Table 8-26.

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Configures the output mode for each high-side driver and heater.

Table 8-26 HS_HEAT_OUT_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	HEAT_CNFG	R/W	0h	Configuration for heater driver. Enables or disables control of heater, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM1 pin control 11b = Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-10	OUT12_CNFG	R/W	0h	Configuration for high-side driver 12. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
9-8	OUT11_CNFG	R/W	0h	Configuration for high-side driver 11. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
7-6	OUT10_CNFG	R/W	0h	Configuration for high-side driver 10. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
5-4	OUT9_CNFG	R/W	0h	Configuration for high-side driver 9. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
3-2	OUT8_CNFG	R/W	0h	Configuration for high-side driver 8. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
1-0	OUT7_CNFG	R/W	0h	Configuration for high-side driver 7. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator

8.2.13 HS_OC_CNFG Register (Offset = 1Eh) [Reset = 1000h]

HS_OC_CNFG is shown in Table 8-27.

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Configures overcurrent threshold for each high-side driver.

Table 8-27 HS_OC_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	OUT11_EC_MODE	R/W	1h	Bit sets high-side OUT11 for independent control through OUT11_CNFG bits or for supply for Electrochromic dirver. 0b = OUT11 is configured as independent high-side driver. Drain of EC FET is connected to PVDD 1b = OUT11 is configured as supply for EC FET
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	OUT12_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 12. 0b = Low current threshold 1b = High current threshold
4	OUT11_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 11. 0b = Low current threshold 1b = High current threshold
3	OUT10_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 10. 0b = Low current threshold 1b = High current threshold
2	OUT9_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 9. 0b = Low current threshold 1b = High current threshold
1	OUT8_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 8. 0b = Low current threshold 1b = High current threshold
0	OUT7_RDSON_MODE	R/W	0h	Configures high-side driver 7 between high RDSON mode and low RDSON mode (for bulb/lamp load). 0b = High RDSON mode (LED driver mode) 1b = Low RDSON mode (bulb/lamp driver mode)

8.2.14 HS_OL_CNFG Register (Offset = 1Fh) [Reset = 0000h]

HS_OL_CNFG is shown in Table 8-28.

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Configures open load threshold for each high-side driver.

Table 8-28 HS_OL_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	OUT12_OLA_TH	R/W	0h	Configures high-side driver 12 open load threshold. 0b = Low threshold 1b = High threshold
12	OUT11_OLA_TH	R/W	0h	Configures high-side driver 11 open load threshold. 0b = Low threshold 1b = High threshold
11	OUT10_OLA_TH	R/W	0h	Configures high-side driver 10 open load threshold. 0b = Low threshold 1b = High threshold
10	OUT9_OLA_TH	R/W	0h	Configures high-side driver 9 open load threshold. 0b = Low threshold 1b = High threshold
9	OUT8_OLA_TH	R/W	0h	Configures high-side driver 8 open load threshold. 0b = Low threshold 1b = High threshold
8	RESERVED	R/W	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	OUT12_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 12.
4	OUT11_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 11.
3	OUT10_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 10.
2	OUT9_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 9.
1	OUT8_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 8.
0	OUT7_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 7.

8.2.15 HS_REG_CNFG1 Register (Offset = 20h) [Reset = 0000h]

HS_REG_CNFG1 is shown in Table 8-29.

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Configures OUT7 ITRIP settings.

Table 8-29 HS_REG_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	OUT7_ITRIP_EN	R/W	0h	Enables ITRIP for high-side driver 7.
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3-2	OUT7_ITRIP_FREQ	R/W	0h	Configures OUT7 ITRIP regulation frequency. 00b = 1.7 kHz 01b = 2.2 kHz 10b = 3 kHz 11b = 4.4 kHz
1-0	OUT7_ITRIP_DG	R/W	0h	Configures OUT7 ITRIP deglitch time. 00b = 48 µs 01b = 40 µs 10b = 32 µs 11b = 24 µs

8.2.16 HS_REG_CNFG2 Register (Offset = 21h) [Reset = 0000h]

HS_REG_CNFG2 is shown in Table 8-30.

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Configures constant current mode for each high-side driver.

Table 8-30 HS_REG_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	OUT12_CCM_TO	R/W	0h	Configures the constant current mode current limit option of high-side output 12. 0b = 350 mA 1b = 450 mA
12	OUT11_CCM_TO	R/W	0h	Configures the constant current mode current limit option of high-side output 11. 0b = 350 mA 1b = 450 mA
11	OUT10_CCM_TO	R/W	0h	Configures the constant current mode current limit option of high-side output 10. 0b = 350 mA 1b = 450 mA
10	OUT9_CCM_TO	R/W	0h	Configures the constant current mode current limit option of high-side output 9. 0b = 350 mA 1b = 450 mA
9	OUT8_CCM_TO	R/W	0h	Configures the constant current mode current limit option of high-side output 8. 0b = 350 mA 1b = 450 mA
8	OUT7_CCM_TO	R/W	0h	Configures the constant current mode current limit option of high-side output 7. CCM values are based on OUT7_RDSON_MODE. If OUT7_RDSON_MODE = 0b: 0b = 250 mA 1b = 330 mA IF OUT7_RDSON_MODE = 1b: 0b = 360 mA 1b = 450 mA
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	OUT12_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 12.
4	OUT11_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 11.
3	OUT10_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 10.
2	OUT9_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 9.
1	OUT8_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 8.
0	OUT7_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 7.

8.2.17 HS_PWM_FREQ_CNFG Register (Offset = 22h) [Reset = 0000h]

HS_PWM_FREQ_CNFG is shown in Table 8-31.

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Configures the frequency for each dedicated PWM generator.

Table 8-31 HS_PWM_FREQ_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-10	PWM_OUT12_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 12. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz
9-8	PWM_OUT11_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 11. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz
7-6	PWM_OUT10_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 10. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz
5-4	PWM_OUT9_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 9. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz
3-2	PWM_OUT8_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 8. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz
1-0	PWM_OUT7_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 7. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz

8.2.18 HEAT_CNFG Register (Offset = 23h) [Reset = 0A3Ch]

HEAT_CNFG is shown in Table 8-32.

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Configures heater driver and fault responses.

Table 8-32 HEAT_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-8	HEAT_VDS_LVL	R/W	Ah	Heater MOSFET VDS monitor protection threshold. 0000b = 0.06 V 00001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.24 V 1001b = 0.28 V 1010b = 0.32 V 1011b = 0.36 V 1100b = 0.4 V 1101b = 0.44 V 1110b = 0.56 V 1111b = 1 V
7-6	HEAT_VDS_MODE	R/W	0h	Heater MOSFET VDS overcurrent monitor fault mode. 00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled.
5-4	HEAT_VDS_BLK	R/W	3h	Heater MOSFET VDS monitor blanking time. 00b = 4 µs 01b = 8 µs 10b = 16 µs 11b = 32 µs
3-2	HEAT_VDS_DG	R/W	3h	Heater MOSFET VDS overcurrent monitor deglitch time. 00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs
1	HEAT_OLP_EN	R/W	0h	Enables heater offline open load detection circuit.
0	RESERVED	R/W	0h	Reserved

8.2.19 EC_CNFG Register (Offset = 24h) [Reset = 0000h]

EC_CNFG is shown in Table 8-33.

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Configures electrochrome driver and fault responses.

Table 8-33 EC_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	ECFB_DIAG	R/W	0h	Enables open-load detection circuit on ECFB. 00b = disable 01b = SC 10b = OLP 11b = disable/reserved
13-12	EC_OUT11_OCP_DG	R/W	0h	OUT11 OCP Deglitch setting when EC_MODE=1 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs
11-10	ECFB_SC_RSEL	R/W	0h	ECFB Diagnostic short-circuit detection options. 00b = 0.5 Ω 01b = 1.0 Ω 10b = 2.0 Ω 11b = 3.0 Ω
9-8	ECFB_OV_DG	R/W	0h	Configures overvoltage fault deglitch time. 00b = 20 µs 01b = 50 µs 10b = 100 µs 11b = 200 µs
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5-4	ECFB_OV_MODE	R/W	0h	Configures ECFB OV fault response for EC driver. 0b = No action 01b = Report ECFB_OV if voltage > 3V longer than EFB_OV_DG time. 10b = Report ECFB_OV if voltage > 3V longer than EFB_OV_DG time, drive ECDRV low with pulldown.
3	EC_FLT_MODE	R/W	0h	Configures overcurrent fault response for EC driver. 0b = Hi-Z EC Driver 1b = Retry with OUT7 ITRIP settings
2	ECFB_LS_PWM	R/W	0h	Enables LS PWM discharge for EC load. 0b = No PWM discharge (Fast discharge) 1b = PWM discharge enabled
1	EC_OLEN	R/W	0h	This bit enables the open load detection circuit during EC discharge. 0b = Open load detection disabled during EC discharge 1b = Open load detection enabled during EC discharge
0	ECFB_MAX	R/W	0h	Configures the maximum target voltage for EC. 0b = 1.2 V 1b = 1.5 V

8.2.20 HS_REG_CNFG3 Register (Offset = 25h) [Reset = 0000h]

HS_REG_CNFG3 is shown in Table 8-34.

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Configures HS ITRIP settings.

Table 8-34 HS_REG_CNFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-10	HS_OUT_ITRIP_FREQ	R/W	0h	ITRIP FREQ settings for OUT8-12 00b - 1.7KHz 01b - 2.2KHz 10b - 3KHz 11b - 4.4KHz
9-8	HS_OUT_ITRIP_DG	R/W	0h	Common ITRIP deglitch settings for OUT8-12 drivers 00b - 48 µs 01b - 40 µs 10b - 32 µs 11b - 24 µs
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	HS_OUT12_ITRIP_EN	R/W	0h	Enables ITRIP for high-side driver 12.
3	HS_OUT11_ITRIP_EN	R/W	0h	Enables ITRIP for high-side driver 11.
2	HS_OUT10_ITRIP_EN	R/W	0h	Enables ITRIP for high-side driver 10.
1	HS_OUT9_ITRIP_EN	R/W	0h	Enables ITRIP for high-side driver 9.
0	HS_OUT8_ITRIP_EN	R/W	0h	Enables ITRIP for high-side driver 8.

8.2.21 SPARE_CNFG2 Register (Offset = 26h) [Reset = 0000h]

SPARE_CNFG2 is shown in Table 8-35.

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Spare configuration register.

Table 8-35 SPARE_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2	RESERVED	R/W	0h	Reserved
1	RESERVED	R/W	0h	Reserved
0	RESERVED	R/W	0h	Reserved

8.2.22 OUT1_HS_MODE_DC Register (Offset = 27h) [Reset = 0000h]

OUT1_HS_MODE_DC is shown in Table 8-36.

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Configures 10 bits for duty cycle

Table 8-36 OUT1_HS_MODE_DC Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9-0	OUT1_DC	R/W	0h	10-bit resolution control of Duty Cycle for dedicated PWM generator for OUT1 with max value of 1022 when OUT1_MODE=1.

8.2.23 OUT2_HS_MODE_DC Register (Offset = 28h) [Reset = 0000h]

OUT2_HS_MODE_DC is shown in Table 8-37.

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Configures 10 bits for duty cycle

Table 8-37 OUT2_HS_MODE_DC Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9-0	OUT2_DC	R/W	0h	10-bit resolution control of Duty Cycle for dedicated PWM generator for OUT2 with max value of 1022 when OUT2_MODE=1.