SLVSHD9A March   2025  – December 2025 DRV8001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RHA package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Sense Output (IPROPI)
      6. 7.4.6 Protection Circuits
        1. 7.4.6.1 Fault Reset (CLR_FLT)
        2. 7.4.6.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.6.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.6.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.6.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.6.6 Thermal Clusters
        7. 7.4.6.7 Watchdog Timer
        8. 7.4.6.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8001-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)

If the voltage across the heater driver VDS overcurrent comparator exceeds the VDS_LVL_HEAT for longer than the tDS_HEAT_DG time, a heater overcurrent condition is detected. The voltage threshold and deglitch time can be adjusted through the HEAT_CNFG register settings.

Table 7-5 Heater VDS Levels
HEAT_VDS_LVL VDS Voltage Level
0000b 0.06V
0001b 0.08V
0010b 0.10V
0011b 0.12V
0100b 0.14V
0101b 0.16V
0110b 0.18V
0111b 0.2V
1000b 0.24V
1001b 0.28V
1010b 0.32V
1011b 0.36V
1100b 0.4V
1101b 0.44V
1110b 0.56V
1111b 1V
Table 7-6 Heater VDS Deglitch Times
HEAT_VDS_DG Time
00b 1μs
01b 2μs
10b 4μs
11b 8μs

There is also a heater MOSFET VDS monitor blanking period that is configured in bit HEAT_VDS_BLK in register HEAT_CNFG. There are four blanking time options:

Table 7-7 Heater VDS Blanking Times
HEAT_VDS_BLK Time
00b 4μs
01b 8μs
10b 16μs
11b 32μs

The heater overcurrent monitor can respond and recover in four different modes set through the HEAT_VDS_MODE register setting.

  • Latched Fault Mode: After detecting the overcurrent event, the gate driver pulldown is enabled, HEAT_VDS and EC_HEAT bits are asserted. After the overcurrent event is removed, the fault state remains latched until CLR_FLT is issued.
  • Cycle by Cycle Mode: After detecting the overcurrent event, the gate driver pulldown is enabled and HEAT_VDS, EC_HEAT and FAULT bits are asserted. EC_HEAT and FAULT status bit in register IC_STAT1 remains asserted until driver control input changes (SPI or PWM). To clear HEAT_VDS bit, a CLR_FLT command must be sent after an input change. If CLR_FLT is issued before an input change, all the status bits remain asserted and driver pulldown stays enabled.
  • Warning Report Only Mode: The heater overcurrent event is reported in the WARN and HEAT_VDS bits. The device takes no action. The warning remains latched until CLR_FLT is issued.
  • Disabled Mode: The heater VDS overcurrent monitors are disabled and do not respond or report.