SLVSHD9A March   2025  – December 2025 DRV8001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RHA package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Sense Output (IPROPI)
      6. 7.4.6 Protection Circuits
        1. 7.4.6.1 Fault Reset (CLR_FLT)
        2. 7.4.6.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.6.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.6.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.6.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.6.6 Thermal Clusters
        7. 7.4.6.7 Watchdog Timer
        8. 7.4.6.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8001-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
7.4.4.5.2 Half-bridge Open Load Detection

When the device is active and waiting for drive commands, there is an open-load detection loop for half-bridges OUT1 - OUT6. The detection scheme sequentially checks the open-load status for each high- and low-side of each half-bridge output and reports the status in bit OUTx_xx_OLA in register HB_STAT2 and WARN bit in register IC_STAT1.

From standby or sleep mode, starting with OUT1, the control loop begins checking the open-load status by comparing the current to the under-current threshold for that half-bridge after completing the open-load filter time. When running in PWM mode, this delay can be configured for 32, 128, 512, or 1024 PWM cycles with bit OUTx_OLA_TH in register HB_OL_CNFG2. The readback takes one extra cycle for example if OUTx_OLA_TH is configured for 32 cycles the value to read back is available at the end of the 33rd cycle. If an output is driven with EN/DIS only (no PWM switching) then the open-load detection delay is 10ms.

Table 7-35 Open Load Detection Cycle Delay
OUTx_OLA_TH Delay Cycle Count
00b 32
01b 128
10b 512
11b 1024

If open-load is detected at the end of the cycle count threshold or 10ms timeout occurs, then bit OUTx_HS_OLA/OUTx_LS_OLA is reported. If no open-load is detected after configured delay cycle count, then the loop moves to the next half-bridge. The loop continues checking each output through OUT6, then goes back to OUT1 to restart the OLA loop. For the open-load check to be valid, the half-bridge open-load detection must be enabled (OUTx_OLA = 1b) and the output OUTx_CNFG must not be disabled. The diagram below shows the OLA scheme:

DRV8001-Q1 Half-bridge Open-Load Active Detection Figure 7-15 Half-bridge Open-Load Active Detection

Any given half-bridge is skipped if any of the following three conditions are met:

  1. OUTx is disabled (OUTx_CNFG = 00b).
  2. Open-load detect is not enabled (OUTx_OLA = 0b) for the half-bridge.
  3. OUTx is OFF for more than 10ms
  4. Both HS_OLA and LS_OLA have already been detected and flagged, or other fault condition on OUTx (overcurrent, over temperature)
With all half-bridge OUTx enabled without PWM, the total loop time can take up to 60ms to cycle through all half-bridges. When a half-bridge is driven individually or sequentially, the loop detects open load within 10ms or more (depending on EN or PWM control frequency). If a half-bridge is driven with a low frequency external PWM signal, the OFF time of the output can exceed the open-load detection window of 10ms, and so the half-bridge reports the status at end of timeout or number of PWM cycles less than 10ms and continue.