SLVSHI4A October   2025  – December 2025 DRV81545

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Clamp Diode, VCLAMP
      2. 6.3.2 Protection Circuits
        1. 6.3.2.1 ILIM Analog Current Limit
          1. 6.3.2.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.2.2 Cut-Off Delay (COD)
        3. 6.3.2.3 Thermal Shutdown (TSD)
        4. 6.3.2.4 Undervoltage Lockout (UVLO)
      3. 6.3.3 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.2.1 ILIM Analog Current Limit

The DRV81545 implements an analog current limit on each output as a protection against short circuits or capacitive loads with large inrush current. If the output stage sees a high-current condition I > ILIM_ACTIVATE, the FET gate drive voltage is reduced to regulate the output current at the ILIM level. This gate drive adjustment operates the FET in the linear region, resulting in a much higher RDS(ON) and dissipating significant power. This current limiting feature (ILIM) is designed to be similar to overcurrent protection, but instead of completely shutting the FET off during an overcurrent event, the current is limited to a safe level until the device overheats.

Figures Figure 6-4 and Figure 6-5 show ILIM reducing the inrush current to a safe level before steady-state continuous current, such as in the case of a capacitive load. This feature provides system-level benefits of reducing PCB trace width and reducing the system power supply capability requirements.

DRV81545 High Startup Current Without Current Limiting ProtectionFigure 6-4 High Startup Current Without Current Limiting Protection
DRV81545 Controlled Startup Current With ILIM Current Limiting ProtectionFigure 6-5 Controlled Startup Current With ILIM Current Limiting Protection

The analog current limit level, ILIM, can be configured with a pull-down resistor on the ILIM pin to GND as shown in Table 6-5. The same value of ILIM is set for all four channels based on RILIM. The current limit condition on one channel does not affect other channels, unless there is an event such as a chip-wide over-temperature.

Table 6-2 Analog Current Limit Level Depending on ILIM Resistor
RILIM RESISTOR BETWEEN ILIM PIN AND GND CURRENT LIMIT LEVEL, ILIM
0 ≤ RLIM< 20kΩ 3A
30kΩ ≤ RLIM ≤ 120kΩ ILIM[A] = 60/RLIM[kΩ]
RLIM≥ 120kΩ ILIM[A] = 60/RLIM[kΩ], can be non-linear

Figure 6-6 shows the active current limit during tTIME_TO_TSD during a short condition with cut-off delay disabled (0kΩ ≤ RCOD < 20kΩ). The cut-off delay feature is explained further in Section 6.3.2.2. After the channel shuts off, the channel retries only after the channel temperature returns to safe level (tTSD – tTSD_HYS). If the channel INx state changes during a ILIM condition the controller responds to the input state change, such as shutting off the output. If the device has shut off due to TSD and the temperature is still above a safe level, the device does not respond to the input state change, meaning the devices does not turn the output back on if the device is still too hot, even if INx is toggled.

DRV81545 Current Limit Response to Short With Thermal Shutdown Based Retry (Cut-Off Delay Disabled) Figure 6-6 Current Limit Response to Short With Thermal Shutdown Based Retry (Cut-Off Delay Disabled)

Figure 6-7 shows a simplified schematic of the analog current limit circuit for each low-side FET.

DRV81545 Analog Current Limit and Sensing Diagram Figure 6-7 Analog Current Limit and Sensing Diagram