SLVSHI4A October   2025  – December 2025 DRV81545

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Clamp Diode, VCLAMP
      2. 6.3.2 Protection Circuits
        1. 6.3.2.1 ILIM Analog Current Limit
          1. 6.3.2.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.2.2 Cut-Off Delay (COD)
        3. 6.3.2.3 Thermal Shutdown (TSD)
        4. 6.3.2.4 Undervoltage Lockout (UVLO)
      3. 6.3.3 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.3 Power Dissipation

Power dissipation in the DRV81545 device is dominated by the power dissipated in the output FET resistance, or RDS(on). Average power dissipation of each FET when running a static load can be roughly estimated by Equation 14:

Equation 14. P = R D S O N × I O U T 2

where

  • P is the power dissipation of one FET
  • RDS(ON) is the resistance of each FET
  • IOUT is equal to the average current drawn by the load.

At start-up and fault conditions, this current is much higher than normal running current; consider these peak currents and duration. When driving more than one load simultaneously, the power in all active output stages must be summed.

The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking.

Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this action into consideration when sizing the heatsink.