The device uses D-CAP4 control architecture to achieve fast load transient response while maintaining ease-of-use. This control system incorporates an internal ripple generation network that emulates inductor current ripple and integrates with the voltage feedback signal, enabling both rapid response and precise output voltage regulation. D-CAP4 allows the use of very low-ESR output capacitors, including multi-layered ceramic capacitors (MLCC) and low-ESR polymer capacitors, without requiring external current sensing, ripple injection, or voltage compensation networks.

Unlike earlier D-CAP2 and D-CAP3 architectures, D-CAP4 employs a fixed ramp amplitude each switching cycle and a forward gain path to improve transient response and reduce pulse frequency jitter, while an error amplifier provides high DC set-point accuracy. A key advantage of D-CAP4 is the ability to minimize loop gain variation across the entire output voltage range, enabling consistent fast load transient response with a single ramp setting. The R-C time-constant of the internal ramp circuit sets the zero frequency of the ramp, similar to other R-C based internal ramp generation architectures. This reduced variation in loop gain eliminates the need for a feedforward capacitor to optimize transient response. Additionally, the fixed ramp amplitude architecture eliminates loop gain variation across input voltage.

The device offers four user-selectable compensation settings through (D4h) COMP. When internal reference DAC target voltages are ≥750mV, the device automatically increases the ramp amplitudes to compensate for higher effective loop gain and maintain stable setpoints for a wider range of reference voltages. SEL_SUMCOMP in (D4h) COMP shows the state of this compensation adjustment. Users can force SEL_SUMCOMP high or low by writing to the override bits in (D4h) COMP. For internal feedback, estimate V_{REF_DAC} by multiplying the output voltage by (29h) VOUT_SCALE_LOOP (for example, V_OUT = 1.6V and VOUT_SCALE_LOOP = 0.5 gives V_{REF_DAC} of 800mV). When using external feedback, V_{REF_DAC} equals the voltage on the VOS/FB pin. Note that the V_{REF_DAC} target only updates when the output is disabled, so crossing the 750mV threshold with (21h) VOUT_COMMAND while the device is regulating does not change the state of SEL_SUMCOMP. Table 7-1 details the available loop compensation settings accessible through the digital interface.

RAMP2 and RAMP3 result in similar loop bandwidth as the ramp amplitudes are similar. The primary difference between these two settings is the ramp zero frequency. The lower ramp zero location for RAMP3 increases phase margin. However, RAMP2 provides faster transient response than RAMP3 because RAMP2 gives higher gain across the entire frequency range due to higher ramp zero location with comparable ramp amplitudes. For most applications, RAMP3 must be used instead of RAMP2. RAMP3 can be used to provide phase boost in applications using an L-C whose double pole frequency allows using RAMP4 but where minimizing jitter is more important than faster transient response. TI recommends using the calculator in the technical documentation section of the TPS544A28 Product Page when evaluating compensation settings and output L-C selection.

For any control topologies supporting no external compensation, there is a minimum range, maximum range, or both, for the output filter the control topologies can support. The output filter used for a typical buck converter is a low-pass L-C circuit. This L-C filter has double pole that Equation 1 shows.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per decade and increases the phase by 90 degrees per decade above the zero frequency.

The inductor and capacitor selected for the output filter must be such that the f_P double pole of Equation 1 is located no higher than the value calculated by using the scaling constants in Table 7-2. Increasing V_REF scales down the f_P(MAX) because the internal DCAP-4 ramp amplitude remains constant. As the reference voltage increases, the relative ramp amplitude decreases, also decreasing the f_P(MAX).

An L-C double pole frequency that violates these guidelines for each setting can be possible, but must be validated in the application with measurements.

After identifying the application requirements, the output inductance is typically designed so the inductor peak-to-peak ripple current is approximately between 15% and 40% of the maximum output current in the application. Choosing very small output capacitance leads to a high frequency L-C double pole which causes the overall loop gain to stay high until the L-C double pole frequency. Given the zero from the internal ripple generation network is a relatively high frequency as well, the loop with very small output capacitance can have too high of a crossover frequency which can cause instability. In general, where reasonable (or smaller) output capacitance is desired, output ripple requirement and load transient requirement can be used to determine the necessary output capacitance for stable operation.

If MLCCs are used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10µF, X5R and 6.3V, the derating by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case is 40% and 4µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the application.

As a simplified rule, if an output capacitor with an ESR zero that is less than 10 × the L-C double pole frequency, TI recommends to ignore when calculating the L-C double pole frequency for stability purposes. The L-C double pole frequency must be recalculated using only the low ESR MLCCs. For more accurate analysis when using mixed type output capacitors, TI recommends simulations or measurements.

For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C double pole frequency is no less than 1/100th of the switching frequency. With this starting point, verify the small signal response on the board and confirm that the phase margin at the loop crossover is greater than 45 degrees. The actual maximum output capacitance can go higher as long as phase margin is greater than 45 degrees. However, a small signal measurement (Bode plot) must be done to confirm the design.

For large output filters with an L-C double pole near 1/100th of the operating frequency, additional phase boost can be required. A feedforward capacitor placed in parallel with R_{FB_HS} can boost the phase when using external feedback. When using internal feedback, the user can adjust the internal loop response with SEL_LC_H in SYS_CFG_USER1. In practice, this can help boost phase margin for large output filters. See also the Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor application note.

Besides boosting the phase, a feedforward capacitor feeds more V_OUT node information into the FB node through AC coupling. This feedforward during load transient event enables faster response of the control loop to a V_OUT deviation. However, this feedforward during steady state operation also feeds more V_OUT ripple and noise into FB. High ripple and noise on FB usually leads to more jitter, or even double-pulse behavior. To determine the final feedforward capacitor value impacts to phase margin, consider load transient performance, ripple, and noise on FB. TI recommends using frequency analysis equipment to measure the crossover frequency and the phase margin.

VIN=12V	VCC = Internal	FSW = 800kHz
LOUT = 1μH	COUT = 5 × 47μF	Load = 250mΩ

Figure 7-1 Simulated Gain vs Ramp Setting with V_OUT = 0.5V and SEL_SUMCOMP = 0

VIN=12V	VCC = Internal	FSW = 800kHz
LOUT = 1μH	COUT = 5 × 47μF	Load = 250mΩ

Figure 7-3 Simulated Gain vs V_REF with RAMP3 and SEL_SUMCOMP = 1

VIN=12V	VCC = Internal	FSW = 800kHz
LOUT = 1μH	COUT = 5 × 47μF	Load = 250mΩ

Figure 7-2 Simulated Phase vs Ramp Setting with V_OUT = 0.5V and SEL_SUMCOMP = 0

VIN=12V	VCC = Internal	FSW = 800kHz
LOUT = 1μH	COUT = 5 × 47μF	Load = 250mΩ

Figure 7-4 Simulated Phase vs V_REF with RAMP3 and SEL_SUMCOMP = 1