SLVSIC6 August   2026 DRV81325-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Transient Thermal Impedance & Current Capability
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
      1. 6.2.1 Control interface / Power input
      2. 6.2.2 Shunt sensing support
      3. 6.2.3 Paralleling of channels
    3. 6.3 Protection Circuits
      1. 6.3.1 Overvoltage clamp
        1. 6.3.1.1 Demagnetization energy capability
      2. 6.3.2 Single pulse clamping capability
      3. 6.3.3 Overcurrent limit
        1. 6.3.3.1 Current limiting when channels paralleled
      4. 6.3.4 Thermal Shutdown (TSD)
        1. 6.3.4.1 Dynamic Overtemperature Stress (ΔTDYN)
        2. 6.3.4.2 Absolute Overtemperature (TSD)
      5. 6.3.5 Undervoltage Lockout (UVLO)
      6. 6.3.6 Summary of STATUS pin response
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
    3. 7.3 Transient thermal performance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Thermal Consideration
      1. 7.5.1 Power Dissipation
      2. 7.5.2 Heatsinking
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Community Resources
    3. 7.3 Trademarks
  10.   Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Typical values are at TA = 25°C , VIN = 5V unless otherwise noted. All limits are over recommended operating conditions, unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES(IN1,IN2)
IINx_norm

Control input current draw in normal operation

INx = 1

25

40

65

µA
IINx_fault

Control input current draw in abnormal operation (Current limit)

INx = 1

400µA

VINx_uvlo_rise

IN undervoltage rising

2.5

2.9

V

VINx__uvlo_fall

IN undervoltage falling

2.3

2.6

V

STATUS OUTPUT(STATUS1, STATUS2)(DRV81325A)
VSTAT_LStatus output low voltage

ISTAT= 1mA

0.4V
ISTAT_H

Status high leakage current

VSTAT = 5V

1

μA
OUTPUT STAGE
RDS(ON)FET on resistanceIO = 1A , TJ = 25°C , VINx=3V, DRV81325A

125

mΩ
IO = 1A , TJ = 25°C, VINx=3V, DRV81325
IO = 1A, TJ = 150°C , VINx=3V, DRV81325A

250

IO = 1A , TJ = 150°C, VINx=3V, DRV81325
RDS(ON)FET on resistanceIO = 1A , TJ = 25°C , VINx=5V, DRV81325A

110

IO = 1A , TJ = 25°C, VINx=5V, DRV81325
IO = 1A, TJ = 150°C , VINx=5V, DRV81325A

220

IO = 1A , TJ = 150°C, VINx=5V, DRV81325
IOFFOff-state leakage current

VOUT = 18 V, TJ = 150°C

5

μA
VF

Body diode forward voltage

IO = -1A

0.8

V

VCLTH_LT

Drain source clamping voltage threshold

IOUT = 10 mA , TJ = -40°C

40

V

VCLAMPDrain source clamping voltageIOUT = 1.5 A , TJ = 150°C

41

45

V

SWITCHING
tRRise timeVLOAD = 13V; RL = 13Ω, VINx=3V

20

30

40

μs
VLOAD = 13V; RL = 13Ω, VINx=5V

20

30

40

tFFall timeVLOAD = 13V; RL = 13Ω, VINx=3V

30

60

120

μs
VLOAD = 13V; RL = 13Ω, VINx=5V1525

50

SRrise

Rising slew rate

VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VINx=3V

0.3

0.5

0.7

V/

μs
VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VINx=5V

0.3

0.5

0.7

SRfall

Falling slew rate

VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VINx=3V

0.1

0.25

0.4

V/

μs
VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VINx=5V

0.3

0.5

0.7

tPD_L_to_H

Propogation Delay , Input Low to Output High

VLOAD = 13V; RL = 13Ω, VINx=3V

20

33

40

μs

VLOAD = 13V; RL = 13Ω, VINx=5V

20

33

40

tPD_H_to_L

Propogation Delay, Input High to Output Low

VLOAD = 13V; RL = 13Ω, VINx=3V

18

25

45

μs

VLOAD = 13V; RL = 13Ω, VINx=5V

18

25

45

PROTECTION CIRCUITS

ILIM

Current limitation value

VINx= 5, TJ = 25°C , DDA package

7.8

10

A

VINx= 5, TJ = 125°C , DDA package

5.5

A

VINx= 5, TJ = 25°C , D package

4.7

6

A

VINx= 5, TJ = 125°C , D package

3

A

TTSD

Thermal shutdown temperatureDie temperature150

175

200

°C
TTSD_hysThermal shutdown temperature

hysteresis

7

°C
TSTAT_reset

Thermal reset of Status

DRV81325A

135

°C

ΔTJ

Dynamic temperature

40

°C

ΔTJ_HYS

Dynamic temperature hysteresis

15

°C

tSTATUS

Overtemperature deglitch on STATUS pinDRV81325A

20

μs

Output timing diagrams

DRV81325-Q1 Output rise/fall timesFigure 5-1 Output rise/fall times
DRV81325-Q1 Propogation delayFigure 5-2 Propogation delay