SLVSIC6 August   2026 DRV81325-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Transient Thermal Impedance & Current Capability
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
      1. 6.2.1 Control interface / Power input
      2. 6.2.2 Shunt sensing support
      3. 6.2.3 Paralleling of channels
    3. 6.3 Protection Circuits
      1. 6.3.1 Overvoltage clamp
        1. 6.3.1.1 Demagnetization energy capability
      2. 6.3.2 Single pulse clamping capability
      3. 6.3.3 Overcurrent limit
        1. 6.3.3.1 Current limiting when channels paralleled
      4. 6.3.4 Thermal Shutdown (TSD)
        1. 6.3.4.1 Dynamic Overtemperature Stress (ΔTDYN)
        2. 6.3.4.2 Absolute Overtemperature (TSD)
      5. 6.3.5 Undervoltage Lockout (UVLO)
      6. 6.3.6 Summary of STATUS pin response
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
    3. 7.3 Transient thermal performance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Thermal Consideration
      1. 7.5.1 Power Dissipation
      2. 7.5.2 Heatsinking
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Community Resources
    3. 7.3 Trademarks
  10.   Mechanical, Packaging, and Orderable Information

6.3.1.1 Demagnetization energy capability

During demagnetization of inductive loads, magnetic energy is dissipated in the DRV813xx-Q1 low-side switch. The equation shows how to calculate the energy for low-side switches when the low-side VDS clamp voltage is VDS_CL , when the load (L, RL ) is carrying current IL and the other end of load is connected to VLOAD:

Equation 1. EAS=VDS_CL×[VLOAD-VDS_CLRL×ln⁡1-RL×ILVLOAD-VDS_CL+IL]×LRL

Under the assumption of RL = 0, this simplifies to

Equation 1. EAS=12×L×IL 2×VDS_CLVDS_CL-VLOAD

The maximum energy, which is converted into heat, is limited by the thermal design of the component. The EAS_sp value provided in Section 5.1 denotes the single pulse energy handling capability per channel, while the EAS_Rep_p value provided in Section 5.1 denotes the repetitive pulse energy handling capability per channel.