SLVSJF0A October   2025  – July 2026 DRV7167

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information_DRV7167A
    5. 5.5 Electrical Characteristics
  7. 6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Mismatch Measurement
    2. 7.2 Slew Rate Measurement
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Inputs
        1. 8.3.1.1 EN/FLT Control
      2. 8.3.2  Dead Time Setting in Single PWM Mode
      3. 8.3.3  Start-up and UVLO
      4. 8.3.4  Synchronous Bootstrap
      5. 8.3.5  Level Shift
      6. 8.3.6  Zero Voltage Detection (ZVD) Reporting
      7. 8.3.7  Slew Rate Control
      8. 8.3.8  Fault Indication
      9. 8.3.9  Overcurrent Protection (OCP)
      10. 8.3.10 Over Temperature Detection (OTD)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap Capacitor
        2. 9.2.2.2 GVDD Bypass Capacitor
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Slew rate plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Information
      1. 12.1.1 Mechanical Data

4 Pin Configuration and Functions

DRV7167 VBN Package,18-Pin VQFN(Top View) Figure 4-1 VBN Package,18-Pin VQFN(Top View)
Pin Functions
PINI/O(1)DESCRIPTION
NAMENO.
DHL/ZVDL1IOIn PWM mode, sets the dead time for high-to-low transition by connecting a resistor to AGND.

In IIM mode, zero-voltage detection output signal to indicate if low-side FET achieves zero-voltage switching in current switching cycle. Note: Do not Tie ZVDL to GVDD.

DLH/ZVDH2IOIn PWM mode, sets the dead time for low-to-high transition by connecting a resistor to AGND.

In IIM mode, zero-voltage detection output signal to indicate if high-side FET achieves zero-voltage switching in current switching cycle.

RDLR3ISets the slew-rate control for LS FET turn-on through resistor to AGND.
RDLF4ISets the slew-rate control for LS FET turn-off through resistor to AGND.

Float this pin to enable PWM mode.

OUT5PSwitching node. Internally connected to HS pin.
PGND6, 17, 18GPower ground. Low-side GaN FET source. Internally connected to low-side GaN FET source.
VM7PInput voltage pin. Internally connected to high-side GaN FET drain.
RDHF8ISets the slew-rate control for HS FET turn-off through resistor to HS.
RDHR9ISets the slew-rate control for HS FET turn-on through resistor to HS. Note: Do not float RDHR pin.
BOOT10PHigh-side gate driver bootstrap rail. Connect bypass capacitor to HS.
HS11PHigh-side GaN FET source connection.
ENIN/HI12IIn PWM mode, enables gate-drive for both high-side and low-side FETs.

In IIM mode, high-side gate driver control input.

PWM/LI13IIn PWM mode, PWM input.

In IIM mode, low-side gate driver control input.

GVDD14P5V device power supply.
AGND15GAnalog ground. Internally connected to low-side GaN FET source.
EN/FLT16IOChip enable and Fault output pin. Connect to microcontoller output or to GVDD through 4.7 kΩ resistor.
(1) I = Input, O = Output, IO = Input/Output, G = Ground, P = Power