SLVSJF0A October   2025  – July 2026 DRV7167

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information_DRV7167A
    5. 5.5 Electrical Characteristics
  7. 6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Mismatch Measurement
    2. 7.2 Slew Rate Measurement
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Inputs
        1. 8.3.1.1 EN/FLT Control
      2. 8.3.2  Dead Time Setting in Single PWM Mode
      3. 8.3.3  Start-up and UVLO
      4. 8.3.4  Synchronous Bootstrap
      5. 8.3.5  Level Shift
      6. 8.3.6  Zero Voltage Detection (ZVD) Reporting
      7. 8.3.7  Slew Rate Control
      8. 8.3.8  Fault Indication
      9. 8.3.9  Overcurrent Protection (OCP)
      10. 8.3.10 Over Temperature Detection (OTD)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap Capacitor
        2. 9.2.2.2 GVDD Bypass Capacitor
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Slew rate plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Information
      1. 12.1.1 Mechanical Data

7.2 Slew Rate Measurement

Figure 7-1 measures OUT node rising and falling slew rate corresponding to HI pulse for selected RDHR and RDHF resistors as shown in Figure 7-5. Slew is calculated from 20% to 80% rise or fall time of the OUT node as per Equation 3.

Equation 3. SlewRDXX=(0.6 × VM) / tRDXX
DRV7167 Slew Rate Measurement for RDHR and RDHFFigure 7-5 Slew Rate Measurement for RDHR and RDHF
DRV7167 Slew Rate Measurement for RDLR and RDLFFigure 7-6 Slew Rate Measurement for RDLR and RDLF