SLVSK12 October   2025 DRV8311-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Secondary Device Mode Timings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Control Modes
        1. 7.3.2.1 6x PWM Mode (DRV8311S-Q1 and DRV8311H-Q1 variants only)
        2. 7.3.2.2 3x PWM Mode (DRV8311S-Q1 and DRV8311H-Q1 variants only)
        3. 7.3.2.3 PWM Generation Mode (DRV8311S-Q1 and DRV8311P-Q1 Variants)
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Four Level Input Pin
      10. 7.3.10 Current Sense Amplifiers
        1. 7.3.10.1 Current Sense Amplifier Operation
        2. 7.3.10.2 Current Sense Amplifier Offset Correction
      11. 7.3.11 Protections
        1. 7.3.11.1 VM Supply Undervoltage Lockout (NPOR)
        2. 7.3.11.2 Under Voltage Protections (UVP)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 OCP Latched Shutdown (OCP_MODE = 010b)
          2. 7.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
          3. 7.3.11.3.3 OCP Report Only (OCP_MODE = 011b)
          4. 7.3.11.3.4 OCP Disabled (OCP_MODE = 111b)
        4. 7.3.11.4 Thermal Protections
          1. 7.3.11.4.1 Thermal Warning (OTW)
          2. 7.3.11.4.2 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI and tSPI Format
  9. 8 DRV8311-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
        2. 9.2.1.2 Driver Propagation Delay and Dead Time
        3. 9.2.1.3 Delay Compensation
        4. 9.2.1.4 Current Sensing and Output Filtering
        5. 9.2.1.5 Application Curves
    3. 9.3 Three Phase Brushless-DC tSPI Motor Control
      1. 9.3.1 Detailed Design Procedure
    4. 9.4 Alternate Applications
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Bulk Capacitance
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
      3. 9.6.3 Thermal Considerations
        1. 9.6.3.1 Power Dissipation and Junction Temperature Estimation
  11. 10Device and Documentation Support
    1. 10.1 Support Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8 DRV8311-Q1 Registers

DRV8311-Q1 Registers lists the memory-mapped registers for the DRV8311-Q1 registers. All register offset addresses not listed in DRV8311-Q1 Registers is considered as reserved locations and the register contents is not modified.

Table 8-1 DRV8311-Q1 Registers
OffsetAcronymRegister NameSection
0hDEV_STS1Device Status 1 RegisterDEV_STS1 Register (Offset = 0h) [Reset = 0080h]
4hOT_STSOver Temperature Status RegisterOT_STS Register (Offset = 4h) [Reset = 0000h]
5hSUP_STSSupply Status RegisterSUP_STS Register (Offset = 5h) [Reset = 0000h]
6hDRV_STSDriver Status RegisterDRV_STS Register (Offset = 6h) [Reset = 0000h]
7hSYS_STSSystem Status RegisterSYS_STS Register (Offset = 7h) [Reset = 0000h]
ChPWM_SYNC_PRDPWM Sync Period RegisterPWM_SYNC_PRD Register (Offset = Ch) [Reset = 0000h]
10hFLT_MODEFault Mode RegisterFLT_MODE Register (Offset = 10h) [Reset = 0115h]
12hSYSF_CTRLSystem Fault Control RegisterSYSF_CTRL Register (Offset = 12h) [Reset = 0515h]
13hDRVF_CTRLDriver Fault Control RegisterDRVF_CTRL Register (Offset = 13h) [Reset = 0030h]
16hFLT_TCTRLFault Timing Control RegisterFLT_TCTRL Register (Offset = 16h) [Reset = 0003h]
17hFLT_CLRFault Clear RegisterFLT_CLR Register (Offset = 17h) [Reset = 0000h]
18hPWMG_PERIODPWM_GEN Period RegisterPWMG_PERIOD Register (Offset = 18h) [Reset = 0000h]
19hPWMG_A_DUTYPWM_GEN A Duty RegisterPWMG_A_DUTY Register (Offset = 19h) [Reset = 0000h]
1AhPWMG_B_DUTYPWM_GEN B Duty RegisterPWMG_B_DUTY Register (Offset = 1Ah) [Reset = 0000h]
1BhPWMG_C_DUTYPWM_GEN C Duty RegisterPWMG_C_DUTY Register (Offset = 1Bh) [Reset = 0000h]
1ChPWM_STATEPWM State RegisterPWM_STATE Register (Offset = 1Ch) [Reset = 0777h]
1DhPWMG_CTRLPWM_GEN Control RegisterPWMG_CTRL Register (Offset = 1Dh) [Reset = 0000h]
20hPWM_CTRL1PWM Control Register 1PWM_CTRL1 Register (Offset = 20h) [Reset = 0007h]
22hDRV_CTRLPredriver control RegisterDRV_CTRL Register (Offset = 22h) [Reset = 0000h]
23hCSA_CTRLCSA Control RegisterCSA_CTRL Register (Offset = 23h) [Reset = 0008h]
3FhSYS_CTRLSystem Control RegisterSYS_CTRL Register (Offset = 3Fh) [Reset = 0000h]

Complex bit access types are encoded to fit into small table cells. DRV8311-Q1 Access Type Codes shows the codes that are used for access types in this section.

Table 8-2 DRV8311-Q1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1 DEV_STS1 Register (Offset = 0h) [Reset = 0080h]

DEV_STS1 is shown in DEV_STS1 Register and described in DEV_STS1 Register Field Descriptions.

Return to the Summary Table.

Device Status 1 Register

Figure 8-1 DEV_STS1 Register
15141312111098
Parity_bitRESERVEDOTP_FLT
R-0hR-0-0hR-0h
76543210
RESETSPI_FLTOCPRESERVEDUVPOTFAULT
R-1hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-3 DEV_STS1 Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-9RESERVEDR-00h Reserved
8OTP_FLTR0h OTP read fault

0h = No OTP read fault is detected

1h = OTP read fault detected

7RESETR1h Supply Power On Reset Status

0h = No power on reset condition is detected

1h = Power-on-reset condition is detected

6SPI_FLTR0h SPI Fault Status

0h = No SPI communication fault is detected

1h = SPI communication fault is detected

5OCPR0h Driver Overcurrent Protection Status

0h = No overcurrent condition is detected

1h = Overcurrent condition is detected

4-3RESERVEDR0h Reserved
2UVPR0h Supply Undervoltage Status

0h = No undervoltage voltage condition is detected on CP, AVDD or VIN_AVDD

1h = Undervoltage voltage condition is detected on CP, AVDD or VIN_AVDD

1OTR0h Overtemperature Fault Status

0h = No overtemperature warning / shutdown is detected

1h = Overtemperature warning / shutdown is detected

0FAULTR0h Device Fault Status

0h = No fault condition is detected

1h = Fault condition is detected

8.2 OT_STS Register (Offset = 4h) [Reset = 0000h]

OT_STS is shown in OT_STS Register and described in OT_STS Register Field Descriptions.

Return to the Summary Table.

Over Temperature Status Register

Figure 8-2 OT_STS Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDOTS_AVDDOTWOTSD
R-0-0hR-0hR-0hR-0h
Table 8-4 OT_STS Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-3RESERVEDR-00h Reserved
2OTS_AVDDR0h AVDD LDO Overtemperature Fault Status

0h = No overtemperature shutdown near AVDD is detected

1h = Overtemperature shutdown near AVDD is detected

1OTWR0h Overtemperature Warning Status

0h = No overtemperature warning is detected

1h = Overtemperature warning is detected

0OTSDR0h Overtemperature Shutdown Fault Status

0h = No overtemperature shutdown is detected

1h = Overtemperature shutdown is detected

8.3 SUP_STS Register (Offset = 5h) [Reset = 0000h]

SUP_STS is shown in SUP_STS Register and described in SUP_STS Register Field Descriptions.

Return to the Summary Table.

Supply Status Register

Figure 8-3 SUP_STS Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDCSAREF_UVCP_UVRESERVEDAVDD_UVRESERVEDVINAVDD_UV
R-0-0hR-0hR-0hR-0-0hR-0hR-0-0hR-0h
Table 8-5 SUP_STS Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-6RESERVEDR-00h Reserved
5CSAREF_UVR0h CSA REF Undervoltage Fault Status

0h = No CSAREF undervoltage is detected

1h = CSAREF undervoltage is detected

4CP_UVR0h Charge Pump Undervoltage Fault Status

0h = No charge pump undervoltage is detected

1h = Charge pump undervoltage is detected

3RESERVEDR-00h Reserved
2AVDD_UVR0h AVDD LDO Undervoltage Fault Status

0h = No AVDD output undervoltage is detected

1h = AVDD output undervoltage is detected

1RESERVEDR-00h Reserved
0VINAVDD_UVR0h VIN_AVDD Undervoltage Fault Status

0h = No AVDD supply input undervoltage is detected

1h = AVDD supply input undervoltage is detected

8.4 DRV_STS Register (Offset = 6h) [Reset = 0000h]

DRV_STS is shown in DRV_STS Register and described in DRV_STS Register Field Descriptions.

Return to the Summary Table.

Driver Status Register

Figure 8-4 DRV_STS Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDOCPC_HSOCPB_HSOCPA_HSRESERVEDOCPC_LSOCPB_LSOCPA_LS
R-0-0hR-0hR-0hR-0hR-0-0hR-0hR-0hR-0h
Table 8-6 DRV_STS Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-7RESERVEDR-00h Reserved
6OCPC_HSR0h Overcurrent Status on High-side MOSFET of OUTC

0h = No overcurrent detected on high-side MOSFET of OUTC

1h = Overcurrent detected on high-side MOSFET of OUTC

5OCPB_HSR0h Overcurrent Status on High-side MOSFET of OUTB

0h = No overcurrent detected on high-side MOSFET of OUTB

1h = Overcurrent detected on high-side MOSFET of OUTB

4OCPA_HSR0h Overcurrent Status on High-side MOSFET of OUTA

0h = No overcurrent detected on high-side MOSFET of OUTA

1h = Overcurrent detected on high-side MOSFET of OUTA

3RESERVEDR-00h Reserved
2OCPC_LSR0h Overcurrent Status on Low-side MOSFET of OUTC

0h = No overcurrent detected on low-side MOSFET of OUTC

1h = Overcurrent detected on low-side MOSFET of OUTC

1OCPB_LSR0h Overcurrent Status on Low-side MOSFET of OUTB

0h = No overcurrent detected on low-side MOSFET of OUTB

1h = Overcurrent detected on low-side MOSFET of OUTB

0OCPA_LSR0h Overcurrent Status on Low-side MOSFET of OUTA

0h = No overcurrent detected on low-side MOSFET of OUTA

1h = Overcurrent detected on low-side MOSFET of OUTA

8.5 SYS_STS Register (Offset = 7h) [Reset = 0000h]

SYS_STS is shown in SYS_STS Register and described in SYS_STS Register Field Descriptions.

Return to the Summary Table.

System Status Register

Figure 8-5 SYS_STS Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDOTPLD_ERRRESERVEDSPI_PARITYBUS_CNTFRM_ERR
R-0-0hR-0hR-0-0hR-0hR-0hR-0h
Table 8-7 SYS_STS Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-5RESERVEDR-00h Reserved
4OTPLD_ERRR0h OTP Read Error

0h = No OTP read error is detected

1h = OTP read error is detected

3RESERVEDR-00h Reserved
2SPI_PARITYR0h SPI Parity Error

0h = No SPI Parity Error is detected

1h = SPI Parity Error is detected

1BUS_CNTR0h SPI Bus Contention Error

0h = No SPI Bus Contention Error is detected

1h = SPI Bus Contention Error is detected

0FRM_ERRR0h SPI Frame Error

0h = No SPI Frame Error is detected

1h = SPI Frame Error is detected

8.6 PWM_SYNC_PRD Register (Offset = Ch) [Reset = 0000h]

PWM_SYNC_PRD is shown in PWM_SYNC_PRD Register and described in PWM_SYNC_PRD Register Field Descriptions.

Return to the Summary Table.

PWM Sync Period Register

Figure 8-6 PWM_SYNC_PRD Register
15141312111098
Parity_bitRESERVEDPWM_SYNC_PRD
R-0hR-0-0hR-0h
76543210
PWM_SYNC_PRD
R-0h
Table 8-8 PWM_SYNC_PRD Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12RESERVEDR-00h Reserved
11-0PWM_SYNC_PRDR0h 12-bit output indicating period of PWM_SYNC signal

8.7 FLT_MODE Register (Offset = 10h) [Reset = 0115h]

FLT_MODE is shown in FLT_MODE Register and described in FLT_MODE Register Field Descriptions.

Return to the Summary Table.

Fault Mode Register

Figure 8-7 FLT_MODE Register
15141312111098
Parity_bitRESERVEDOTPFLT_MODE
R-0hR-0-0hR/W-1h
76543210
SPIFLT_MODEOCP_MODEUVP_MODEOTSD_MODE
R/W-0hR/W-1hR/W-1hR/W-1h
Table 8-9 FLT_MODE Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-9RESERVEDR-00h Reserved
8OTPFLT_MODER/W1h System Fault Mode.

0h = OTP read fault is enabled

1h = OTP read fault is disabled

7SPIFLT_MODER/W0h SPI Fault mode

0h = SPI Fault is enabled

1h = SPI Fault is disabled

6-4OCP_MODER/W1h Overcurrent Protection Fault mode

0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry time (in ms)

1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry time (in ms)

2h = Report on nFault, predriver HiZ, Latched Fault

3h = Report on nFault, No action on predriver

4h = Reserved

5h = Reserved

6h = Reserved

7h = Disabled

3-2UVP_MODER/W1h Undervoltage Protection Fault mode

0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry time (in ms)

1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry time (in ms)

2h = Reserved

3h = Reserved

1-0OTSD_MODER/W1h Overtemperature Fault mode

0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry time (in ms)

1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry time (in ms)

2h = Reserved

3h = Reserved

8.8 SYSF_CTRL Register (Offset = 12h) [Reset = 0515h]

SYSF_CTRL is shown in SYSF_CTRL Register and described in SYSF_CTRL Register Field Descriptions.

Return to the Summary Table.

System Fault Control Register

Figure 8-8 SYSF_CTRL Register
15141312111098
Parity_bitRESERVEDOTAVDD_ENOTW_ENRESERVED
R-0hR-0-0hR/W-1hR/W-0hR-0-4h
76543210
RESERVEDCSAREFUV_ENRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-4hR/W-0hR/W-1hR-0-0hR/W-1hR-0-0hR/W-1h
Table 8-10 SYSF_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-11RESERVEDR-00h Reserved
10OTAVDD_ENR/W1h AVDD Overtemperature Fault Enable

0h = Overtemperature protection near AVDD is disabled

1h = Overtemperature protection near AVDD is enabled

9OTW_ENR/W0h Overtemperature Warning Fault Enable

0h = Over temperature warning reporting on nFAULT is disabled

1h = Over temperature warning reporting on nFAULT is enabled

8-6RESERVEDR-04h Reserved
5CSAREFUV_ENR/W0h CSAREF Undervoltage Fault Enable

0h = CSAREF undervoltage lockout is disabled

1h = CSAREF undervoltage lockout is enabled

4RESERVEDR/W1h Reserved
3RESERVEDR-00h Reserved
2RESERVEDR/W1h Reserved
1RESERVEDR-00h Reserved
0RESERVEDR/W1h Reserved

8.9 DRVF_CTRL Register (Offset = 13h) [Reset = 0030h]

DRVF_CTRL is shown in DRVF_CTRL Register and described in DRVF_CTRL Register Field Descriptions.

Return to the Summary Table.

Driver Fault Control Register

Figure 8-9 DRVF_CTRL Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDOCP_DEGOCP_TBLANKRESERVEDOCP_LVL
R-0-0hR/W-3hR/W-0hR-0-0hR/W-0h
Table 8-11 DRVF_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-6RESERVEDR-00h Reserved
5-4OCP_DEGR/W3h OCP Deglitch time

0h = OCP deglitch time is 0.2 µs

1h = OCP deglitch time is 0.5 µs

2h = OCP deglitch time is 0.8 µs

3h = OCP deglitch time is 1 µs

3-2OCP_TBLANKR/W0h OCP Blanking time

0h = OCP blanking time is 0.2 µs

1h = OCP blanking time is 0.5 µs

2h = OCP blanking time is 0.8 µs

3h = OCP blanking time is 1 µs

1RESERVEDR-00h Reserved
0OCP_LVLR/W0h OCP Level Settings

0h = OCP level is 9 A (TYP)

1h = OCP level is 5 A (TYP)

8.10 FLT_TCTRL Register (Offset = 16h) [Reset = 0003h]

FLT_TCTRL is shown in FLT_TCTRL Register and described in FLT_TCTRL Register Field Descriptions.

Return to the Summary Table.

Fault Timing Control Register

Figure 8-10 FLT_TCTRL Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDSLOW_TRETRYFAST_TRETRY
R-0-0hR/W-0hR/W-3h
Table 8-12 FLT_TCTRL Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-4RESERVEDR-00h Reserved
3-2SLOW_TRETRYR/W0h Slow Recovery Retry Time from Fault Condition

0h = 0.5s

1h = 1s

2h = 2s

3h = 5s

1-0FAST_TRETRYR/W3h Fast Recovery Retry Time from Fault Condition

0h = 0.5ms

1h = 1ms

2h = 2ms

3h = 5ms

8.11 FLT_CLR Register (Offset = 17h) [Reset = 0000h]

FLT_CLR is shown in FLT_CLR Register and described in FLT_CLR Register Field Descriptions.

Return to the Summary Table.

Fault Clear Register

Figure 8-11 FLT_CLR Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDFLT_CLR
R-0-0hW-0h
Table 8-13 FLT_CLR Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-1RESERVEDR-00h Reserved
0FLT_CLRW0h Clear Fault

0h = No clear fault command is issued

1h = To clear the latched fault bits. This bit automatically resets after being written.

8.12 PWMG_PERIOD Register (Offset = 18h) [Reset = 0000h]

PWMG_PERIOD is shown in PWMG_PERIOD Register and described in PWMG_PERIOD Register Field Descriptions.

Return to the Summary Table.

PWM_GEN Period Register

Figure 8-12 PWMG_PERIOD Register
15141312111098
Parity_bitRESERVEDPWM_PRD_OUT
R-0hR-0-0hR/W-0h
76543210
PWM_PRD_OUT
R/W-0h
Table 8-14 PWMG_PERIOD Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12RESERVEDR-00h Reserved
11-0PWM_PRD_OUTR/W0h 12-bit Period for output PWM signals in PWM Generation Mode

8.13 PWMG_A_DUTY Register (Offset = 19h) [Reset = 0000h]

PWMG_A_DUTY is shown in PWMG_A_DUTY Register and described in PWMG_A_DUTY Register Field Descriptions.

Return to the Summary Table.

PWM_GEN A Duty Register

Figure 8-13 PWMG_A_DUTY Register
15141312111098
Parity_bitRESERVEDPWM_DUTY_OUTA
R-0hR-0-0hR/W-0h
76543210
PWM_DUTY_OUTA
R/W-0h
Table 8-15 PWMG_A_DUTY Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12RESERVEDR-00h Reserved
11-0PWM_DUTY_OUTAR/W0h 12-bit Duty Cycle for Phase A output in PWM Generation Mode

8.14 PWMG_B_DUTY Register (Offset = 1Ah) [Reset = 0000h]

PWMG_B_DUTY is shown in PWMG_B_DUTY Register and described in PWMG_B_DUTY Register Field Descriptions.

Return to the Summary Table.

PWM_GEN B Duty Register

Figure 8-14 PWMG_B_DUTY Register
15141312111098
Parity_bitRESERVEDPWM_DUTY_OUTB
R-0hR-0-0hR/W-0h
76543210
PWM_DUTY_OUTB
R/W-0h
Table 8-16 PWMG_B_DUTY Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12RESERVEDR-00h Reserved
11-0PWM_DUTY_OUTBR/W0h 12-bit Duty Cycle for Phase B output in PWM Generation Mode

8.15 PWMG_C_DUTY Register (Offset = 1Bh) [Reset = 0000h]

PWMG_C_DUTY is shown in PWMG_C_DUTY Register and described in PWMG_C_DUTY Register Field Descriptions.

Return to the Summary Table.

PWM_GEN C Duty Register

Figure 8-15 PWMG_C_DUTY Register
15141312111098
Parity_bitRESERVEDPWM_DUTY_OUTC
R-0hR-0-0hR/W-0h
76543210
PWM_DUTY_OUTC
R/W-0h
Table 8-17 PWMG_C_DUTY Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12RESERVEDR-00h Reserved
11-0PWM_DUTY_OUTCR/W0h 12-bit Duty Cycle for Phase C output in PWM Generation Mode

8.16 PWM_STATE Register (Offset = 1Ch) [Reset = 0777h]

PWM_STATE is shown in PWM_STATE Register and described in PWM_STATE Register Field Descriptions.

Return to the Summary Table.

PWM State Register

Figure 8-16 PWM_STATE Register
15141312111098
Parity_bitRESERVEDPWMC_STATE
R-0hR-0-0hR/W-7h
76543210
RESERVEDPWMB_STATERESERVEDPWMA_STATE
R-0-0hR/W-7hR-0-0hR/W-7h
Table 8-18 PWM_STATE Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-11RESERVEDR-00h Reserved
10-8PWMC_STATER/W7h Phase C Driver Output control

0h = High Side is OFF, Low Side is OFF

1h = High Side is OFF, Low Side is forced ON

2h = High Side is forced ON, Low Side is OFF

3h = Reserved

4h = Reserved

5h = High Side is OFF, Low Side PWM

6h = High Side PWM, Low Side is OFF

7h = High Side PWM, Low Side !PWM

7RESERVEDR-00h Reserved
6-4PWMB_STATER/W7h Phase B Driver Output control

0h = High Side is OFF, Low Side is OFF

1h = High Side is OFF, Low Side is forced ON

2h = High Side is forced ON, Low Side is OFF

3h = Reserved

4h = Reserved

5h = High Side is OFF, Low Side PWM

6h = High Side PWM, Low Side is OFF

7h = High Side PWM, Low Side !PWM

3RESERVEDR-00h Reserved
2-0PWMA_STATER/W7h Phase A Driver Output control

0h = High Side is OFF, Low Side is OFF

1h = High Side is OFF, Low Side is forced ON

2h = High Side is forced ON, Low Side is OFF

3h = Reserved

4h = Reserved

5h = High Side is OFF, Low Side PWM

6h = High Side PWM, Low Side is OFF

7h = High Side PWM, Low Side !PWM

8.17 PWMG_CTRL Register (Offset = 1Dh) [Reset = 0000h]

PWMG_CTRL is shown in PWMG_CTRL Register and described in PWMG_CTRL Register Field Descriptions.

Return to the Summary Table.

PWM_GEN Control Register

Figure 8-17 PWMG_CTRL Register
15141312111098
Parity_bitRESERVEDPWM_ENPWMCNTR_MODE
R-0hR-0-0hR/W-0hR/W-0h
76543210
PWM_OSC_SYNCSPICLK_FREQ_SYNCSPISYNC_ACRCY
R/W-0hR/W-0hR/W-0h
Table 8-19 PWMG_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-11RESERVEDR-00h Reserved
10PWM_ENR/W0h Enable 3X Internal mode PWM Generation

0h = PWM_GEN disabled

1h = PWM_GEN enabled

9-8PWMCNTR_MODER/W0h PWM Gen counter mode

0h = Up and Down

1h = Up

2h = Down

3h = No action

7-5PWM_OSC_SYNCR/W0h Oscillator synchronization and PWM_SYNC control

0h = Oscillator synchronization is disable

1h = PWM_SYNC_PRD indicates period of PWM_SYNC signal and can be used to calibrate PWM period

2h = PWM_SYNC used to set PWM period

3h = Oscillator synchronization is disable

4h = Oscillator synchronization is disable

5h = PWM_SYNC used for oscillator synchronization (only 20 kHz frequency supported)

6h = PWM_SYNC used for oscillator synchronization and setting PWM period (only 20 kHz frequency supported)

7h = SPI Clock pin SCLK used for oscillator synchronization (Configure SPICLK_FREQ_SYNC)

4-2SPICLK_FREQ_SYNCR/W0h SPI Clock Frequency for synchronizing the Oscillator

0h = 1 MHz

1h = 1.25 MHz

2h = 2 MHz

3h = 2.5 MHz

4h = 4 MHz

5h = 5 MHz

6h = 8 MHz

7h = 10 MHz

1-0SPISYNC_ACRCYR/W0h Number of SPI Clock Cycle require for synchronizing the Oscillator

0h = 512 Clock Cycles (1%)

1h = 256 Clock Cycles (1%)

2h = 128 Clock Cycles (1%)

3h = 64 Clock Cycles (2%)

8.18 PWM_CTRL1 Register (Offset = 20h) [Reset = 0007h]

PWM_CTRL1 is shown in PWM_CTRL1 Register and described in PWM_CTRL1 Register Field Descriptions.

Return to the Summary Table.

PWM Control Register 1

Figure 8-18 PWM_CTRL1 Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDSSC_DISPWM_MODE
R-0-0hR/W-1hR/W-3h
Table 8-20 PWM_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-3RESERVEDR-00h Reserved
2SSC_DISR/W1h Disable Spread Spectrum Modulation for internal Oscillator

0h = Spread spectrum modulation is enabled

1h = Spread spectrum modulation is disabled

1-0PWM_MODER/W3h PWM mode selection (The reset setting in DRV8311-Q1S is 00b and in DRV8311-Q1P is 11b)

0h = 6x mode

1h = 6x mode

2h = 3x mode

3h = PWM Generation mode

8.19 DRV_CTRL Register (Offset = 22h) [Reset = 0000h]

DRV_CTRL is shown in DRV_CTRL Register and described in DRV_CTRL Register Field Descriptions.

Return to the Summary Table.

Predriver control Register

Figure 8-19 DRV_CTRL Register
15141312111098
Parity_bitRESERVEDRESERVED
R-0hR-0-0hR/W-0h
76543210
DLYCMP_ENTDEAD_CTRLRESERVEDSLEW_RATE
R/W-0hR/W-0hR-0-0hR/W-0h
Table 8-21 DRV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12RESERVEDR-00h Reserved
11-8RESERVEDR/W0h Reserved
7DLYCMP_ENR/W0h Driver Delay Compensation enable

0h = Driver Delay Compensation is disabled

1h = Driver Delay Compensation is enabled

6-4TDEAD_CTRLR/W0h Deadtime insertion control

0h = No deadtime (Handshake Only)

1h = 200ns

2h = 400ns

3h = 600ns

4h = 800ns

5h = 1us

6h = 1.2us

7h = 1.4us

3-2RESERVEDR-00h Reserved
1-0SLEW_RATER/W0h Slew rate settings

0h = Slew rate is 35 V/µs

1h = Slew rate is 75 V/µs

2h = Slew rate is 180 V/µs

3h = Slew rate is 230 V/µs

8.20 CSA_CTRL Register (Offset = 23h) [Reset = 0008h]

CSA_CTRL is shown in CSA_CTRL Register and described in CSA_CTRL Register Field Descriptions.

Return to the Summary Table.

CSA Control Register

Figure 8-20 CSA_CTRL Register
15141312111098
Parity_bitRESERVED
R-0hR-0-0h
76543210
RESERVEDCSA_ENRESERVEDCSA_GAIN
R-0-0hR/W-1hR-0-0hR/W-0h
Table 8-22 CSA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-4RESERVEDR-00h Reserved
3CSA_ENR/W1h Current Sense Amplifier Enable

0h = Current Sense Amplifier is disabled

1h = Current Sense Amplifier is enabled

2RESERVEDR-00h Reserved
1-0CSA_GAINR/W0h Current Sense Amplifier Gain settings

0h = CSA gain is 0.25 V/A

1h = CSA gain is 0.5 V/A

2h = CSA gain is 1 V/A

3h = CSA gain is 2 V/A

8.21 SYS_CTRL Register (Offset = 3Fh) [Reset = 0000h]

SYS_CTRL is shown in SYS_CTRL Register and described in SYS_CTRL Register Field Descriptions.

Return to the Summary Table.

System Control Register

Figure 8-21 SYS_CTRL Register
15141312111098
Parity_bitWRITE_KEYRESERVEDRESERVED
R-0hW-0hR-0-0hR/W-0h
76543210
REG_LOCKSPI_PENRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-23 SYS_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15Parity_bitR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12WRITE_KEYW0h 0x5 Write Key Specific to this register.
11-9RESERVEDR-00h Reserved
8RESERVEDR/W0h Reserved
7REG_LOCKR/W0h Register Lock Bit

0h = Registers Unlocked

1h = Registers Locked

6SPI_PENR/W0h Parity Enable for both SPI and tSPI

0h = Parity Disabled

1h = Parity Enabled

5-4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2-0RESERVEDR/W0h Reserved