SLVSK12 October   2025 DRV8311-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Secondary Device Mode Timings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Control Modes
        1. 7.3.2.1 6x PWM Mode (DRV8311S-Q1 and DRV8311H-Q1 variants only)
        2. 7.3.2.2 3x PWM Mode (DRV8311S-Q1 and DRV8311H-Q1 variants only)
        3. 7.3.2.3 PWM Generation Mode (DRV8311S-Q1 and DRV8311P-Q1 Variants)
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Four Level Input Pin
      10. 7.3.10 Current Sense Amplifiers
        1. 7.3.10.1 Current Sense Amplifier Operation
        2. 7.3.10.2 Current Sense Amplifier Offset Correction
      11. 7.3.11 Protections
        1. 7.3.11.1 VM Supply Undervoltage Lockout (NPOR)
        2. 7.3.11.2 Under Voltage Protections (UVP)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 OCP Latched Shutdown (OCP_MODE = 010b)
          2. 7.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
          3. 7.3.11.3.3 OCP Report Only (OCP_MODE = 011b)
          4. 7.3.11.3.4 OCP Disabled (OCP_MODE = 111b)
        4. 7.3.11.4 Thermal Protections
          1. 7.3.11.4.1 Thermal Warning (OTW)
          2. 7.3.11.4.2 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI and tSPI Format
  9. 8 DRV8311-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
        2. 9.2.1.2 Driver Propagation Delay and Dead Time
        3. 9.2.1.3 Delay Compensation
        4. 9.2.1.4 Current Sensing and Output Filtering
        5. 9.2.1.5 Application Curves
    3. 9.3 Three Phase Brushless-DC tSPI Motor Control
      1. 9.3.1 Detailed Design Procedure
    4. 9.4 Alternate Applications
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Bulk Capacitance
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
      3. 9.6.3 Thermal Considerations
        1. 9.6.3.1 Power Dissipation and Junction Temperature Estimation
  11. 10Device and Documentation Support
    1. 10.1 Support Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.9.1 Logic Level Input Pin (Internal Pulldown)

Figure 7-23 shows the input structure for the logic levels pins INHx, INLx, nSLEEP, SCLK and SDI. The input can be driven with an external resistor to GND or an external logic voltage supply.TI recommends to pull these pins low in device sleep mode to reduce leakage current through the internal pull-down resistors.

DRV8311-Q1 Logic-Level Input Pin StructureFigure 7-23 Logic-Level Input Pin Structure