SLVSLM8 May   2026 BQ78709-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ78709-Q1
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Coulomb Counter
    10. 6.10 Coulomb Counter Digital Filter
    11. 6.11 Current Wake Detector
    12. 6.12 Analog-to-Digital Converter
    13. 6.13 Cell Voltage Measurement Accuracy
    14. 6.14 Cell Balancing
    15. 6.15 Internal Temperature Sensor
    16. 6.16 Thermistor Measurement
    17. 6.17 Hardware Overtemperature Detector
    18. 6.18 Internal Oscillator
    19. 6.19 Charge and Discharge FET Drivers
    20. 6.20 Comparator-Based Protection Subsystem
    21. 6.21 Timing Requirements - I2C Interface, 100kHz Mode
    22. 6.22 Timing Requirements - I2C Interface, 400kHz Mode
    23. 6.23 Timing Diagram
    24. 6.24 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage ADC
      2. 7.4.2  Coulomb Counter and Digital Filters
      3. 7.4.3  Protection FET Drivers
      4. 7.4.4  Voltage References
      5. 7.4.5  Multiplexer
      6. 7.4.6  LDOs
      7. 7.4.7  Standalone Versus Host Interface
      8. 7.4.8  ALERT Pin Operation
      9. 7.4.9  Low Frequency Oscillator
      10. 7.4.10 I2C Serial Communications Interface
    5. 7.5 Measurement Subsystem
      1. 7.5.1 Voltage Measurement
        1. 7.5.1.1 Voltage ADC Scheduling
        2. 7.5.1.2 Unused VC Pins
        3. 7.5.1.3 General Purpose ADCIN Functionality
      2. 7.5.2 Current Measurement and Charge Integration
      3. 7.5.3 Internal Temperature Measurement
      4. 7.5.4 Thermistor Temperature Measurement
      5. 7.5.5 Factory Trim and Calibration
    6. 7.6 Protection Subsystem
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 CHG Detector
      4. 7.6.4 Cell Open-Wire Protection
      5. 7.6.5 Diagnostic Checks
    7. 7.7 Cell Balancing
    8. 7.8 Device Operational Modes
      1. 7.8.1 Overview of Operational Modes
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.19 Charge and Discharge FET Drivers

Typical values stated where TA = 25°C and VBAT = 25.9V, min/max values stated where TA = -40°C to 125°C and VBAT = 3V to 38.5V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V(FETON_DSG)DSG driver enabledVREGSRC ≥ 12V, CL= 20nF10.511.213V
V(FETON_CHG)CHG driver enabledVREGSRC ≥ 12V, CL= 20nF1010.812V
V(FETON_LOBAT_DSG)DSG driver enabledVREGSRC < 12V, CL = 20nFVREGSRC – 1VREGSRCV
V(FETON_LOBAT_CHG)CHG driver enabledVREGSRC < 12V, CL = 20nFVREGSRC – 1.75VREGSRCV
t(CHG_ON)CHG FET driver rise timeCHG CL = 20nF, RGATE = 100Ω, VREGSRC = 12V, 0.5V to 5V5085µs
t(DSG_ON)DSG FET driver rise timeDSG CL = 20nF, RGATE = 100Ω, VREGSRC = 12V, 0.5V to 5V3555µs
t(CHG_OFF)CHG FET driver fall timeCHG CL = 20nF, RGATE = 100Ω, VREGSRC = 12V, 80% to 20% of V(FETON_CHG)2435µs
t(DSG_OFF)DSG FET driver fall timeDSG CL = 20nF, RGATE = 100Ω, VREGSRC = 12V, 80% to 20% of V(FETON_DSG)23µs
I(CHG_ON)CHG FET driver output currentCHG enabled and pin held at 8V, VREGSRC = 12V1mA
I(DSG_ON)DSG FET driver output currentDSG enabled and pin held at 8V, VREGSRC = 12V1.56mA
R(DSG_OFF)DSG FET driver off resistanceDSG off and pin held at 100mV1530Ω
V(CHG_DETECT)CHG detector thresholdCHG pin voltage rising1.21.8V
V(CHG_DET_HYS)CHG detector hysteresis0.95V