SLVSLZ3 August   2026 TLV612901

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting
      2. 7.3.2 Switching Frequency and Spread Spectrum Function
    4. 7.4 Device Functional Modes
      1. 7.4.1  Enable and Start-Up
      2. 7.4.2  Operation Mode Setting
      3. 7.4.3  Bypass Mode
      4. 7.4.4  Boost Control Operation
      5. 7.4.5  Auto PFM Mode
      6. 7.4.6  Forced PWM Mode
      7. 7.4.7  Ultrasonic Mode
      8. 7.4.8  Output Discharge
      9. 7.4.9  Undervoltage Lockout
      10. 7.4.10 Current Limit Operation
      11. 7.4.11 Output Short-to-Ground Protection
      12. 7.4.12 Overvoltage Protection
      13. 7.4.13 Thermal Shutdown
      14. 7.4.14 Power-Good Indication Status
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multi-Read and Multi-Write
  9. 8 Register Maps
    1. 8.1 DeviceID Register
    2. 8.2 CONFIG Register
    3. 8.3 VOUTFLOORSET Register
    4. 8.4 ILIMBSTSET Register
    5. 8.5 VOUTROOFSET Register
    6. 8.6 STATUS Register
    7. 8.7 ILIMPTSET Register
    8. 8.8 BSTLOOP Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV612901 With 2.5V – 4.85V VIN, 5.0V VOUT, 3A Output Current
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection
          2. 9.2.1.2.2 Output Capacitor
          3. 9.2.1.2.3 Input Capacitor
          4. 9.2.1.2.4 Checking Loop Stability
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Information
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     79

9.4.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high current, layout is an important design step. If the layout is not carefully done, the regulator can suffer from instability and noise problems. Because the TLV612901 operates with very fast switching rise and fall times, high-frequency noise radiation (such as EMI) can be generated. Therefore, proper layout of the high-frequency switching path is critical. During layout, minimize the length and area of all traces connected to the SW pin, and use a ground plane under the switching regulator. This action helps minimize interlayer coupling and optimize the high-frequency switching path.

The input capacitor must be close to the VIN pin and PGND pin to reduce the Iinput supply ripple. The power paths of VOUT, output capacitor and PGND must be as small as possible to reduce parasitic inductance.

Due to the device high power density, thermal management must be carefully considered during layout design. The SW, VOUT, and PGND pins, which improve the thermal capabilities of the package, must be soldered to a large copper polygon. Additionally, using thermal vias underneath the SW pin can further improve thermal performance.

Additionally, consider the effects of PCB parasitics during layout. Figure 9-16 shows the continuous current path and discontinuous current path in TLV612901. The blue solid line represents the continuous current path and the red dashed line represents the discontinuous current path. Figure 9-17 shows the PCB parasitic inductors in discontinuous current path. The loop formed by power MOSFET Q1, power MOSFET Q2, output capacitor COUT must be minimized as short as possible because the PCB parasitic inductors in these high di/dt current paths generate high voltage spikes at output and across power MOSFETs. The spikes and ringing at switch node SW is the source of EMI and can cause power MOSFET overvoltage damage. To minimize the influences of PCB parasitic inductors Lpara1 and Lpara2, a low ESL and ESR X5R or X7R dielectric ceramic capacitor COUT1 is better to be placed as close as possible to the VOUT pin and GND pin of TLV612901.

TLV612901 Continuous and Discontinuous Current PathsFigure 9-16 Continuous and Discontinuous Current Paths
TLV612901 PCB Parasitic Inductors in Discontinuous Current PathsFigure 9-17 PCB Parasitic Inductors in Discontinuous Current Paths