SLVSMQ4 September   2026 TPS7H5101-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP+
        1. 7.3.1.1 Load Transients
        2. 7.3.1.2 On-Time Control
        3. 7.3.1.3 Switching Frequency
        4. 7.3.1.4 Droop Regulation
        5. 7.3.1.5 Ramp Compensation
        6. 7.3.1.6 Undershoot Reduction (USR)
        7. 7.3.1.7 Overshoot Reduction (OSR)
        8. 7.3.1.8 Current Sensing and Current Sharing
        9. 7.3.1.9 Blanking Time (BLANK)
      2. 7.3.2  PWM Signals
      3. 7.3.3  Remote Sensing and Setting VOUT
      4. 7.3.4  Input Voltage (VIN)
      5. 7.3.5  VLDO
      6. 7.3.6  Voltage Reference (VREF)
      7. 7.3.7  Enable (EN)
      8. 7.3.8  Power Good (PG)
      9. 7.3.9  Turn-On Behavior
        1. 7.3.9.1 Soft-Start (SS)
      10. 7.3.10 Current Monitor Output (ISUM)
      11. 7.3.11 Overcurrent Protection
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 PMBus General Description
      2. 7.5.2 Write Byte
      3. 7.5.3 Read Byte
      4. 7.5.4 Send Byte
      5. 7.5.5 Packet Error Checking (PEC)
      6. 7.5.6 Additional Faults
      7. 7.5.7 PMBus Command Overview
      8. 7.5.8 PMBus Address Selection
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Current Limit Threshold
        3. 9.2.2.3 Load-Line Setting
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Loop Compensation
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     76

7.5.5 Packet Error Checking (PEC)

Packet Error Checking (PEC) can optionally be utilized to provide error checking on data transmissions. If the TPS7H5101 receiver receives data from the controller that does not match the calculated PEC, the TPS7H5101 performs a NACK the of the PEC byte. Additionally, the command is not acted upon and the CML bit is set in the STATUS_BYTE register.

If the controller provided clock pulses are provided before a STOP, PEC is used. If the STOP is issued without extra clock pulses, PEC is not used. Though the PEC is optional, utilization of this feature is recommended for robust and reliable data transmissions.