SLVUCF3 March   2022 DRA829V , LP8764-Q1 , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 TO_ACTIVE
      6. 6.3.6 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Initialization
    2. 7.2 Moving Between States; ACTIVE and RETENTION
      1. 7.2.1 ACTIVE
      2. 7.2.2 RETENTION
    3. 7.3 Entering and Exiting Standby
    4. 7.4 Entering and Existing LP_STANDBY
    5. 7.5 Runtime Customization
  9. 8References

5.8 Interrupt Settings

These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed though I2C after startup.

Table 5-8 Interrupt NVM Settings
Register NameField NameTPS65941213-Q1LP876411B4-Q1
ValueDescriptionValueDescription
FSM_TRIG_MASK_1GPIO1_FSM_MASK0x1Masked0x1Masked
GPIO1_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO2_FSM_MASK0x1Masked0x1Masked
GPIO2_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO3_FSM_MASK0x1Masked0x1Masked
GPIO3_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO4_FSM_MASK0x1Masked0x1Masked
GPIO4_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
FSM_TRIG_MASK_2GPIO5_FSM_MASK0x1Masked0x1Masked
GPIO5_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO6_FSM_MASK0x1Masked0x1Masked
GPIO6_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO7_FSM_MASK0x1Masked0x1Masked
GPIO7_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO8_FSM_MASK0x1Masked0x1Masked
GPIO8_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
FSM_TRIG_MASK_3GPIO9_FSM_MASK0x1Masked0x1Masked
GPIO9_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO10_FSM_MASK0x1Masked0x1Masked
GPIO10_FSM_MASK_POL0x0Low; Masking sets signal value to '0'0x0Low; Masking sets signal value to '0'
GPIO11_FSM_MASK0x1Masked
GPIO11_FSM_MASK_POL0x0Low; Masking sets signal value to '0'
MASK_BUCK1_2BUCK1_ILIM_MASK0x0Interrupt generated0x0Interrupt generated
BUCK1_OV_MASK0x0Interrupt generated0x0Interrupt generated
BUCK1_UV_MASK0x0Interrupt generated0x0Interrupt generated
BUCK2_ILIM_MASK0x0Interrupt generated0x0Interrupt generated
BUCK2_OV_MASK0x0Interrupt generated0x0Interrupt generated
BUCK2_UV_MASK0x0Interrupt generated0x0Interrupt generated
MASK_BUCK3_4BUCK3_ILIM_MASK0x0Interrupt generated0x0Interrupt generated
BUCK3_OV_MASK0x0Interrupt generated0x0Interrupt generated
BUCK3_UV_MASK0x0Interrupt generated0x0Interrupt generated
BUCK4_OV_MASK0x0Interrupt generated0x0Interrupt generated
BUCK4_UV_MASK0x0Interrupt generated0x0Interrupt generated
BUCK4_ILIM_MASK0x0Interrupt generated0x0Interrupt generated
MASK_BUCK5BUCK5_ILIM_MASK0x0Interrupt generated
BUCK5_OV_MASK0x0Interrupt generated
BUCK5_UV_MASK0x0Interrupt generated
MASK_LDO1_2LDO1_OV_MASK0x0Interrupt generated
LDO1_UV_MASK0x0Interrupt generated
LDO2_OV_MASK0x0Interrupt generated
LDO2_UV_MASK0x0Interrupt generated
LDO1_ILIM_MASK0x0Interrupt generated
LDO2_ILIM_MASK0x0Interrupt generated
MASK_LDO3_4LDO3_OV_MASK0x0Interrupt generated
LDO3_UV_MASK0x0Interrupt generated
LDO4_OV_MASK0x0Interrupt generated
LDO4_UV_MASK0x0Interrupt generated
LDO3_ILIM_MASK0x0Interrupt generated
LDO4_ILIM_MASK0x0Interrupt generated
MASK_VMONVCCA_OV_MASK0x1Interrupt not generated.0x1Interrupt not generated.
VCCA_UV_MASK0x1Interrupt not generated.0x1Interrupt not generated.
MASK_GPIO1_8_FALLGPIO1_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO2_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO3_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO4_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO5_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO6_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO7_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO8_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
MASK_GPIO1_8_RISEGPIO1_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO2_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO3_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO4_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO5_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO6_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO7_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO8_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
MASK_GPIO9_11 / MASK_GPIO9_10GPIO9_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO9_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO10_FALL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO11_FALL_MASK0x1Interrupt not generated.
GPIO10_RISE_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GPIO11_RISE_MASK0x1Interrupt not generated.
MASK_STARTUPNPWRON_START_MASK0x1Interrupt not generated.
ENABLE_MASK0x0Interrupt generated0x1Interrupt not generated.
FSD_MASK0x1Interrupt not generated.0x1Interrupt not generated.
SOFT_REBOOT_MASK0x0Interrupt generated0x0Interrupt generated
MASK_MISCTWARN_MASK0x0Interrupt generated0x0Interrupt generated
BIST_PASS_MASK0x0Interrupt generated0x0Interrupt generated
EXT_CLK_MASK0x1Interrupt not generated.0x1Interrupt not generated.
MASK_MODERATE_ERRBIST_FAIL_MASK0x0Interrupt generated0x0Interrupt generated
REG_CRC_ERR_MASK0x0Interrupt generated0x0Interrupt generated
SPMI_ERR_MASK0x0Interrupt generated0x0Interrupt generated
NPWRON_LONG_MASK0x1Interrupt not generated.
NINT_READBACK_MASK0x0Interrupt generated0x0Interrupt generated
NRSTOUT_READBACK_ MASK0x0Interrupt generated0x1Interrupt not generated.
MASK_FSM_ERRIMM_SHUTDOWN_MASK0x0Interrupt generated0x0Interrupt generated
MCU_PWR_ERR_MASK0x0Interrupt generated0x0Interrupt generated
SOC_PWR_ERR_MASK0x0Interrupt generated0x0Interrupt generated
ORD_SHUTDOWN_MASK0x0Interrupt generated0x0Interrupt generated
MASK_COMM_ERRCOMM_FRM_ERR_MASK0x0Interrupt generated0x0Interrupt generated
COMM_CRC_ERR_MASK0x0Interrupt generated0x0Interrupt generated
COMM_ADR_ERR_MASK0x0Interrupt generated0x0Interrupt generated
I2C2_CRC_ERR_MASK0x0Interrupt generated0x1Interrupt not generated.
I2C2_ADR_ERR_MASK0x0Interrupt generated0x1Interrupt not generated.
MASK_READBACK_ERREN_DRV_READBACK_ MASK0x0Interrupt generated0x1Interrupt not generated.
NRSTOUT_SOC_ READBACK_MASK0x0Interrupt generated0x1Interrupt not generated.
MASK_ESMESM_SOC_PIN_MASK0x1Interrupt not generated.
ESM_SOC_RST_MASK0x1Interrupt not generated.
ESM_SOC_FAIL_MASK0x1Interrupt not generated.
ESM_MCU_PIN_MASK0x1Interrupt not generated.0x1Interrupt not generated.
ESM_MCU_RST_MASK0x1Interrupt not generated.0x1Interrupt not generated.
ESM_MCU_FAIL_MASK0x1Interrupt not generated.0x1Interrupt not generated.
GENERAL_REG_1PFSM_ERR_MASK0x0Interrupt generated0x0Interrupt generated
  1. The VCCA_OV_MASK and VCCA_UV_MASK are cleared in both PMICs after the completing BOOT_BIST but before starting the sequence, Section 6.3.5.