SLVUCI5A April   2023  – June 2025 AM6526 , AM6528 , AM6548 , TPS6594-Q1

 

  1.   1
  2.   PDN-0C User's Guide for Powering AM65x with the TPS6594-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety Systems
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  10. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  11. 8References
  12. 9Revision History

5.11 Interface Settings

These settings detail the default interface, interface configurations, and device addresses. These settings cannot be changed after device startup.

Table 5-11 Interface NVM Settings
Register Name Field Name TPS65941319-Q1
Value Description
SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C
I2C1_SPI_CRC_EN 0x0 CRC disabled
I2C2_CRC_EN 0x0 CRC disabled
I2C1_ID_REG I2C1_ID 0x48 0x48
I2C2_ID_REG I2C2_ID 0x12 0x12