SLVUCI5A April   2023  – June 2025 AM6526 , AM6528 , AM6548 , TPS6594-Q1

 

  1.   1
  2.   PDN-0C User's Guide for Powering AM65x with the TPS6594-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety Systems
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  10. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  11. 8References
  12. 9Revision History

6.2 PFSM Triggers

As shown in Figure 6-1, there are various triggers that can enable a state transition between configured states. Table 6-1 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority (I2C_3). Active triggers of higher priority block triggers of lower priority and the associated sequence.

Table 6-1 State Transition Triggers
Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed
Immediate Shutdown 0 True False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM SAFE(1) TO_SAFE_SEVERE
MCU Power Error 1 True False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM SAFE(1) TO_SAFE
Orderly Shutdown 2 True False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM SAFE(1) TO_SAFE_ORDERLY
OFF Request 4(9) False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM STANDBY(2) TO_STANDBY
WDOG Error 5 False True ACTIVE ACTIVE ACTIVE_TO_WARM
ESM MCU Error 6 False True ACTIVE ACTIVE
ESM SOC Error 7 False True ACTIVE Pwr SOC Error ESM_SOC_ERROR
WDOG Error 8 False True MCU ONLY MCU ONLY MCU_TO_WARM
ESM MCU Error 9 False True MCU ONLY MCU ONLY
SOC Power Error 10 False False ACTIVE MCU ONLY PWR_SOC_ERR
I2C_1 bit is high(3) 11 False True ACTIVE, MCU ONLY No State Change Execute RUNTIME BIST
I2C_2 bit is high(3) 12 False True ACTIVE, MCU ONLY No State Change Enable I2C CRC on I2C1 and I2C2 on all devices.(4)
ON Request 13 False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM ACTIVE TO_ACTIVE
WKUP1 goes high 14 False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM ACTIVE
NSLEEP1 and NSLEEP2 are high(5) 15 False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM ACTIVE
MCU ON Request 16 False False STANDBY, ACTIVE(7), MCU ONLY, Suspend-to-RAM MCU ONLY TO_MCU
WKUP2 goes high 17 False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM MCU ONLY
NSLEEP1 goes low and NSLEEP2 goes high(5) 18 False False ACTIVE, MCU ONLY, Suspend-to-RAM MCU ONLY
NSLEEP1 goes low and NSLEEP2 goes low(5) 19 False False ACTIVE, MCU ONLY Suspend-to-RAM TO_RETENTION
NSLEEP1 goes high and NSLEEP2 goes low(5) 20 False False ACTIVE, MCU ONLY Suspend-to-RAM
I2C_0 bit goes high(3) 21(8) False False STANDBY, ACTIVE, MCU ONLY LP_STANDBY(2) TO_STANDBY
I2C_3 bit goes high(3) 22(8) False False ACTIVE, MCU ONLY No State Change Devices are prepared for OTA NVM update.(6)
(1) From the SAFE state, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in Table 5-10). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the data sheet for more details.
(2) If the LP_STANDBY_SEL bit is set (see RTC_CTRL_2, in Table 5-10), then the PFSM transitions to the hardware FSM state of LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the device as determined by the means of entering LP_STANDBY. Refer to the data sheet for more details.
(3) I2C_0, I2C_1, I2C_2 and I2C_3 are self-clearing triggers.
(4) Enabling the I2C CRC, enables the CRC on both I2C1 and I2C2, however, the I2C2 is disabled for 2ms after the CRC is enabled. Be aware when using the watchdog Q&A before enabling I2C CRC. The recommendation is to enable the I2C CRC first, and then after 2ms, start the watchdog Q&A.
(5) NSLEEP1 and NSLEEP2 of the primary PMIC can be accessed through the GPIO pin or through a register bit. If either the register bit or the GPIO pin is pulled high, the NSLEEPx value is read as a high logic level.
(6) After completion of an OTA update, the processor is required to initiate a reset of the PMICs to apply the new NVM settings.
(7) When in the ACTIVE mode, the ON Request to MCU ONLY trigger cannot be accessed while other higher priority triggers, like NSLEEP1=NSLEEP2=HIGH, are still active.
(8) Trigger IDs 21 and 22 are not available until the NSLEEP bits are masked: NSLEEP2_MASK=NSLEEP1_MASK=1.
(9) Trigger IDs 3, 23, and 24 are enabled and activated by the power sequences and are not shown. These triggers are used to manage the transition between the PFSM and the FSM.