SLVUD68B March   2025  – October 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Connection Descriptions
      1. 2.1.1 Connections and Test Points
      2. 2.1.2 Jumper Configurations
  8. 3Implementation Results
    1. 3.1 Variable Resistor for CS and CL
      1. 3.1.1 Current Sense Resistor
      2. 3.1.2 Adjustable Current Limit
  9. 4Hardware Design Files
    1. 4.1 HCXX-BASE-EVM and 2HC08-MOD-EVM Schematic
    2. 4.2 HCXX-BASE-EVM and 2HC08-MOD-EVM Assembly Drawings and Layout
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6Revision History

2.1.2 Jumper Configurations

Jumper Function, Settings
J1 Input diode bypass
J2 Open-load detection pull-up configuration (OUT1)
J3 Diode and TVS for PWM-controlled inductive loads (OUT1)
J4 Module connection ILIM and VOUT1 (left)
J5 Module connection SNS, FLT, and VOUT2 (right)
J6 GND network bypass
J7 RILIM bypass
J8 Open-load detection pull-up configuration (OUT2)
J9 Connect 2 and 3 to enable LDO
J10 Diode and TVS for PWM-controlled inductive loads (OUT2)
J11 Connect 2 and 3 to power EN1 with 5V from LDO
J12 Connect 2 and 3 to power EN2 with 5V from LDO
J13 Connect 2 and 3 to power DIAG_EN with 5V from LDO
J14 Connect 2 and 3 to power SEL with 5V from LDO
J15 LDO voltage output (+5V)
J16 LDO voltage input (VBB)