SLVUDB7 June   2025 TPS7H5020-SEP

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Primary Side Regulation
    2. 2.2 Connector Descriptions
    3. 2.3 Best Practices
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Soft Startup
    3. 3.3 Voltage Ripple on VOUT
    4. 3.4 Load Step
    5. 3.5 Frequency Response
    6. 3.6 Efficiency
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7Related Documentation

Connector Descriptions

Table 2-1 provides the connector descriptions for the TPS7H5020FLYEVM.

Table 2-1 Connector Descriptions
REFERENCE DESIGNATORFUNCTION

J1

PS_PVIN

Power stage input connectors

J2

PGND

J3

VOUT

Power output connectors

J4

GND

J5

IC_VIN

Controller power input connectors

J6

PGND

J7

Np

Compact probe tip connector

J8

Ns

J9

VOUT

TP1

IC_VIN

Test point

TP2

IC_PVIN

TP3

VLDO

TP4

BODE

TP5

SYNC

TP6

SS

TP7

EN

TP8

COMP

TP9

REFCAP

TP10

PS_PVIN

TP11

VOUT

TP12

CS_ILIM

TP14, TP15, TP16, TP17, TP18, TP19, TP21, TP22

GND