SLVUDV8 May   2026

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1  Power Requirements
      1. 2.1.1 VBAT / VSUP
      2. 2.1.2 VDD
      3. 2.1.3 VCC
      4. 2.1.4 VIO
    2. 2.2  Crystal Oscillator
    3. 2.3  CAN
    4. 2.4  SPI
      1. 2.4.1 nCS
      2. 2.4.2 SCLK
      3. 2.4.3 SDI
      4. 2.4.4 SDO
    5. 2.5  Interrupt (nINT)
    6. 2.6  Wake Request (nWKRQ)
    7. 2.7  Reset (RST)
    8. 2.8  Status LEDs
    9. 2.9  Setup
      1. 2.9.1 Jumper Configuration
      2. 2.9.2 Connecting to a Host MCU/SPI Tool
      3. 2.9.3 CAN Bus Connection
      4. 2.9.4 SPI Communication
    10. 2.10 Jumper Information
  7. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 Board Layout
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1. 4.1 Trademarks

2.4.1 nCS

This input pin is used to select the device for a SPI transaction. The pin is active low, so while nCS is high the SDO pin of the device is high impedance allowing a SPI bus to be shared with other devices. When nCS is low the SDO driver is activated and communication can be started. The nCS pin must be held low for the duration of the SPI transaction. A special feature on this device allows the SDO pin to immediately show the Global Fault Flag on a falling edge of nCS. There are two pins on the EVM can be used for the SPI Chip Select defined as SPI_CS. Both of these pins are supported with the header pin 13 connected to the TCAN4572-Q1 nCS pin by default. If there is a conflict with this pin, the other supported chip select pin can be used by removing the 0Ω resistor (R30) and installing the resistor on R31 instead. These pins are labeled on the nCS_0 and nCS_1 next to pins 12 and 13 of the board-to-board headers.

Note:

The Chip Select signal must transition back to a high following the end of the data transaction and cannot be held low indefinitely as is sometimes common practice when only a single device is on the SPI bus. There are 2 primary reasons for this:

  1. The Global Status Register (byte) is always shifted out on the SDO pin for every SPI transaction starting with the first clock cycle following the chip select high-to-low transition.
  2. The device counts the number of bits received on the SDI pin which must be a multiple of 32 bits between the chip select transition to low at the beginning of the transaction and then back to high at the completion of the transaction. If the number of bits is not a multiple of 32 bits, the last word of the transfer is ignored and the SPIERR flag is set.