SLVUDV8 May   2026

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1  Power Requirements
      1. 2.1.1 VBAT / VSUP
      2. 2.1.2 VDD
      3. 2.1.3 VCC
      4. 2.1.4 VIO
    2. 2.2  Crystal Oscillator
    3. 2.3  CAN
    4. 2.4  SPI
      1. 2.4.1 nCS
      2. 2.4.2 SCLK
      3. 2.4.3 SDI
      4. 2.4.4 SDO
    5. 2.5  Interrupt (nINT)
    6. 2.6  Wake Request (nWKRQ)
    7. 2.7  Reset (RST)
    8. 2.8  Status LEDs
    9. 2.9  Setup
      1. 2.9.1 Jumper Configuration
      2. 2.9.2 Connecting to a Host MCU/SPI Tool
      3. 2.9.3 CAN Bus Connection
      4. 2.9.4 SPI Communication
    10. 2.10 Jumper Information
  7. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 Board Layout
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1. 4.1 Trademarks

2.4.4 SDO

This pin is high impedance until the SPI output is enabled using nCS. Once the SPI is enabled by a low on nCS, the SDO is immediately driven high or low showing the Global Fault Flag status which is also the first bit (bit 32) to be shifted out if the SPI is clocked. Once SCLK begins, on the first low to high edge of the clock the SDO retains the Global Fault Flag which is bit 31 of the shift. On the first falling edge of SCLK, the shifting out of the data continues with each falling edge on SCLK until all 32 bits have been shifted out the shift register. Pin 14 of the board-to-board header is used for the SPI SDO as is defined as SPI_MISO.

In test mode this pin is used as an RXD output pin for testing the CAN transceiver and referenced as RXD_INT_PHY.