SLYT863 April   2025 LM5066I

 

  1.   1
  2. 1 Introduction
  3. 2 3
  4. 3 Challenges in designing a hot-swap circuit for a 48V AI server
  5. 4 Challenge No. 1: Turnoff delay during an output short-circuit
  6. 5 Challenge No. 2: False gate turn-off during a load transient
  7. 6 Challenge No. 3: Parallel resonance during controlled (slow) turn-on
  8. 7 Proposed circuit enhancements
  9. 8 Improving the turn-off response
  10. 9 Overcoming false turn-off for dynamic loads
  11. 10Damping parasitic oscillations
  12. 11Design guidelines and component selection
  13. 12Cdv/dt discharge circuit
  14. 13Conclusion
  15. 14References
  16. 15Related Websites

3 Challenges in designing a hot-swap circuit for a 48V AI server

It’s interesting to look at how hot-swap circuit configurations have evolved over the years. A hot-swap solution consists of three main components: a N-channel metal-oxide semiconductor field-effect transistor (MOSFET) that serves as the main power control switch; a sense resistor that measures the current; and the hot-swap controller, which includes a current-sense amplifier completing the loop to control the MOSFET’s pass current.

As shown in Figure 2, you can use a single MOSFET-based hot-swap solution for low-power designs. Fundamentally, the hot-swap controller comes with current- and power-limiting functionalities to limit the inrush and fault currents while ensuring the MOSFET’s safe operating area (SOA). These functionalities are good enough to design low-power (<500W) hot-swap solutions.

Traditional power-limiting hot-swap circuit. Figure 2 Traditional power-limiting hot-swap circuit.
Hot-swap circuit with GATE slew-rate control. Figure 3 Hot-swap circuit with GATE slew-rate control.
Hot-swap circuit with local discharge path for Cdv/dt. Figure 4 Hot-swap circuit with local discharge path for Cdv/dt.

With the increase in digital load, the system needs a higher output capacitance (>470µF), requiring parallel MOSFETs to support steady-state current and the adoption of output-voltage slew-rate control [1] to keep the MOSFET within its SOA.

In the output-voltage slew-rate control method, capacitor Cdv/dt placed across GATE-GND (see Figure 3) limits the slew-rate of the gate and output voltages, which limits the inrush current. MOSFETs can handle more energy when the power dissipation in them is reduced and spread over longer durations. Therefore, as the output capacitance increases, you need a higher Cdv/dt to reduce both the inrush current and power dissipation in the MOSFET during startup.

A higher Cdv/dt interferes with the turnoff process, however, the hot-swap controller has limited pulldown strength. This necessitates a local P-channel N-channel P-channel (PNP)-based discharge circuit for Cdv/dt, as shown in Figure 4. During startup, Cdv/dt controls slew-rate in the same way, but during a turnoff event, the Q1 PNP transistor activates and discharges Cdv/dt locally. Diode D1 blocks the discharge of Cdv/dt into the GATE pin, which reduces the stress on the GATE pin and also ensures proper operation of the controller.

In AI-powered graphics processing unit applications, the hot-swap solution has to support currents around 150A and must support high-frequency, high slew-rate load transients, which present three new challenges.