SNAA400 March   2025 CDC6C , LMK6C , LMK6D , LMK6H , LMK6P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2BAW Overview
    1. 2.1 BAW Oscillator Advantages
    2. 2.2 BAW Oscillator Overview
  6. 3LMK6C Clocking Sitara AM64 Jitter Test
    1. 3.1 Jitter Test Set Up
  7. 4Generic Guide for Clocking AM6x and TDA4x Families
  8. 5Summary
  9. 6References

Generic Guide for Clocking AM6x and TDA4x Families

This section highlights different TI processor families and the respective clocking requirements. All of the processors listed in Table 4-1 have the same VIL, VIH and frequency stability requirement from the clock reference input with majority difference being the frequency and start up time required. Table 4-2 lists BAW oscillator clock recommendation as well as the oscillator's corresponding performance specification.

Table 4-1 Processor Clock Requirements
Processor Device # of External High-frequency oscillators Frequency (MHz) VDD (V) Start up time (ms) VIL (V) (max) VIH (V) (min) Stability (ppm)
AM62x 1 25 1.8 4 0.35x VDD 0.65xVDD ±501, ±1002
AM64 1 25 1.8 4
AM67 1 25 1.8 4
TDA4VEN

TDA4AEN

1 25 1.8 4
AM68 1 19.2, 20, 24, 25, 26, 27 1.8 9.8
AM69 1 19.2, 20, 24, 25, 26, 27 1.8, 3.3 9.8
TDA4VM (Q1)

DRA829

2 19.2, 20, 24, 25, 26, 27 1.8 9.5
DRA821 1 19.2, 20, 24, 25, 26, 27 1.8 9.5
TDA4VH-Q1

TDA4AH-Q1

TDA4VP-Q1

TDA4AP-Q1

1 19.2, 20, 24, 25, 26, 27 1.8 9.5
TDA4VE-Q1

TDA4AL-Q1

TDA4VL-Q1

1 19.2, 20, 24, 25, 26, 27 1.8 9.5
Ethernet RGMII and RMII using derived clock
Ethernet RGMII and RMII not used
Table 4-2 Clock Recommendation for Processors
Processor Device Clock Part Number Frequency Support Range (MHz) VDD (V) VIL (V) (max) VIH(V) (min) Stability (ppm) Startup time max (ms)

AM62x

AM64

AM67

TDA4VEN

TDA4AEN

AM68

AM69

TDA4VM (Q1) DRA829

DRA821

TDA4VH-Q1

TDA4AH-Q1

TDA4VP-Q1

TDA4AP-Q1

TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1

CDC6C 250kHz to 200MHz 1.8V to 3.3V 0.6V 1.3V ±25 3ms
LMK6C 1MHz to 200MHz 1.8V

2.5V to 3.3V

0.6V 1.3V ±25 5ms