SNAA400 March 2025 CDC6C , LMK6C , LMK6D , LMK6H , LMK6P
On the TMDS64EVM a 25MHz LVCMOS oscillator is used as an input to a CDCLVC1310 clock buffer, which is then fed into EXT_REFCLK 1 of the AM64x device. This external refclk is the frequency reference for the internal PLL and clock distribution path. The AM64x device is then configured to route the internal system clock through the output of a GPO pin. The output clock phase noise performance is measured on a phase noise analyzer, and the time-domain jitter characteristics are measured using a DPOJET tool on an oscilloscope.
Jitter performance was measured using both a quartz oscillator to generate the 25MHz refclk as well as the LMK6C BAW oscillator. With LMK6C, the output clock had a 10 to 15dB noise reduction in the frequency band of approximately 100Hz to 500kHz. Spurious tones in the range of 10kHz to 100kHz are mostly likely the result of frequency mixing with other high-frequency noise sources, such as switching voltage regulators. Spurious tones had the same power with both reference frequency sources. Time-domain jitter also showed improvements with LMK6C, especially in terms of cycle-cycle jitter.
Figure 3-1 Quartz Test Block
Diagram
Figure 3-2 LMk6C Test Block
Diagram
Figure 3-3 Quartz Oscillator GPO7 Phase
Noise Plot
Figure 3-4 LMK6C Oscillator GPO7 Phase
Noise Plot| Quartz (ps) | LMK6C (ps) | Quartz and LMK6C Delta (ps) | |
|---|---|---|---|
| RMS Jitter | 45.7694 | 20.0778 | 25.6916 |
| Period Jitter (pk – pk) | 59.265 | 59.126 | 0.139 |
| Period Jitter (std. dev) | 6.7860 | 6.4285 | 0.3575 |
| N-cycle Jitter (pk-pk) | 170.49 | 151.05 | 19.44 |
| N-cycle Jitter (std. dev) | 18.695 | 16.896 | 1.799 |