For maximum EMI mitigation, arrange the PCB stackup to have the clock signal and power traces routed as a stripline (Figure 3-1). Surrounding these high energy sources with ground aids in field containment. Figure 3-2 shows an example of an 8-layer stackup. This example uses Layers 1, 3, and 6 for power and signal traces, surrounding each of those layers with ground planes. While this alone does not fully encompass the traces, this stackup does cover a majority of the surface area, helping to limit radiated EMI.

In addition to layer order, it's crucial to consider how the material characteristics impact trace impedance. The trace width and stackup must work to properly impedance match the traces for the output type being used. For example, LVCMOS typically requires 50Ω trace impedance, while LP-HCSL typically uses 85Ω or 100Ω. When the device and signal layer are not impedance matched, this transition can lead to large EMI spurs. Most PCB software and manufacturers have tools that are able to assist in this. If vias are being used to route the clock trace to a different layer, the impedance of the vias must be taken into account as well.