SNAA408 April   2025 LMK3H0102

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Output Recommendations
    1. 2.1 Differential vs. Single-Ended
    2. 2.2 Slew Rate
    3. 2.3 Spread Spectrum Clocking
  6. 3PCB Design
    1. 3.1 Stackup
    2. 3.2 Power Filtering
    3. 3.3 Avoid Bottlenecking
    4. 3.4 Strategic Via Placements
      1. 3.4.1 Distributing Power Concentrations
        1. 3.4.1.1 Via Sizes
        2. 3.4.1.2 Pads and Pours
      2. 3.4.2 Shielding and Stitching Vias
  7. 4Minimize Possible Antennas
    1. 4.1 Stubs
    2. 4.2 Net Pours
  8. 5Summary
  9. 6References

2.1 Differential vs. Single-Ended

Clocking waveforms tend to have a very high slew rate. This harsh change in voltage is prone to causing large EMI spikes, both at the output frequency and at subsequent harmonics. 25MHz, for example, is likely to have EMI spurs at 25MHz, 50MHz (2nd harmonic), 75MHz (3rd harmonic), and so on. While generating these outputs, harmonics are unavoidable, therefore choosing the proper output type helps mitigate the power of the spurs.

Using a differential output type, such as LVDS or HCSL, is the best case. Differential signals use both a P and N trace, with each trace being 180 degrees out of phase with the other. When P is HIGH, N is LOW, and vice versa (Figure 2-1). Additionally, differential signals are routed very close together throughout the PCB from the clock generator to the end device. This pattern and short distance serve to efficiently minimize the EMI impact of an individual trace.


P and N Traces

Figure 2-1 P and N Traces

We can apply the same method to single-ended output types, such as CMOS. Single-ended output types do not have the same P and N relation as differential signals do; typically only the P or N trace is utilized. But many clocking devices such as the LMK3C0105 can produce two single-ended signals 180 degrees out of phase with each other from a single output channel block. We can use this to our advantage by trying to mimic differential signals as closely as possible. Routing the traces as a differential pair allows for the best EMI performance. If only one half of the LVCMOS pair is being used, then route both traces and terminate the unused trace as close to the receiver as possible. If the LVCMOS pair is being used for two different receivers, create a frequency plan and PCB layout that allows for the clocking pair to be routed as differentially as possible.


Differential Pair Symmetry

Figure 2-2 Differential Pair Symmetry

When using CMOS, this is also important to consider the trace length. Longer traces for this output type require more power, which in turn creates larger EMI output spurs. This is best to use lower power output types whenever possible, whether differential or single-ended (for example, LVCMOS instead of CMOS or LP-HCSL instead of HCSL).