SNAA408 April   2025 LMK3H0102

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Output Recommendations
    1. 2.1 Differential vs. Single-Ended
    2. 2.2 Slew Rate
    3. 2.3 Spread Spectrum Clocking
  6. 3PCB Design
    1. 3.1 Stackup
    2. 3.2 Power Filtering
    3. 3.3 Avoid Bottlenecking
    4. 3.4 Strategic Via Placements
      1. 3.4.1 Distributing Power Concentrations
        1. 3.4.1.1 Via Sizes
        2. 3.4.1.2 Pads and Pours
      2. 3.4.2 Shielding and Stitching Vias
  7. 4Minimize Possible Antennas
    1. 4.1 Stubs
    2. 4.2 Net Pours
  8. 5Summary
  9. 6References

2.3 Spread Spectrum Clocking

Spread Spectrum Clocking (SSC) is the most commonly used tactic to mitigate this source of EMI. SSC is able to reduce the peak amplitude of a digital clock signal by shifting the frequency in a controlled manner, thereby distributing the energy in the frequency domain. This does not, however, affect the amplitude of the clock in the time domain. Center-Spread SSC spreads the energy evenly on either side of the target frequency. Down-Spread SSC only spreads the energy to frequencies below the target. Both versions of SSC can vary in intensity. Figure 2-3 shows the results for 0% (blue), ±0.5% (green), ±1%(cyan) and ±2% (red) center-spread SSC. Clocking devices such as the CDCE6214 and the LMK3H family have SSC capability.


100MHz Output With 0%, ±0.5%, ±1%, and ±2% SSC

Figure 2-3 100MHz Output With 0%, ±0.5%, ±1%, and ±2% SSC

More information can be found in the Spread Spectrum Clocking Using the CDCS502/503, application note.