SNAS787 Data sheet

Table 7-1 lists the CDCDB2000 registers. All register locations not listed in Table 7-1 must be considered as reserved locations and the register contents must not be modified.

Table 7-1 CDCDB2000 Registers

Address	Acronym	Register Name	Section
0h	OECR1	Output Enable Control 1	Go
1h	OECR2	Output Enable Control 2	Go
2h	OECR3	Output Enable Control 3	Go
3h	OERDBK	Output Enable Read Back	Go
4h	SBRDBK	SBEN Read Back	Go
5h	VDRREVID	Vendor/Revision Identification	Go
6h	DEVID	Device Identification	Go
7h	BTRDCNT	Byte Read Count Control	Go
8h	SBIMSK1	Side-Band Interface Override Control 1	Go
9h	SBIMSK2	Side-Band Interface Override Control 2	Go
Ah	SBIMSK3	Side-Band Interface Override Control 3	Go

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 CDCDB2000 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.1.1 OECR1 Register (Address = 0h) [reset = 78h]

OECR1 is shown in Table 7-3.

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The OECR1 register contains bits that enable or disable individual output clock channels [19:16]

Table 7-3 OECR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	Output Enable, CK19	R/W	1h	This bit controls the output enable signal for output channel CK19_P/CK19_N. 0h = Output Disabled 1h = Output Enabled
5	Output Enable, CK18	R/W	1h	This bit controls the output enable signal for output channel CK18_P/CK18_N. 0h = Output Disabled 1h = Output Enabled
4	Output Enable, CK17	R/W	1h	This bit controls the output enable signal for output channel CK17_P/CK17_N. 0h = Output Disabled 1h = Output Enabled
3	Output Enable, CK16	R/W	1h	This bit controls the output enable signal for output channel CK16_P/CK16_N. 0h = Output Disabled 1h = Output Enabled
2-0	RESERVED	R	0h	Reserved

7.1.2 OECR2 Register (Address = 1h) [reset = FFh]

OECR2 is shown in Table 7-4.

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The OECR2 register contains bits that enable or disable individual output clock channels [7:0]

Table 7-4 OECR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	Output Enable, CK7	R/W	1h	This bit controls the output enable signal for output channel CK7_P/CK7_N. 0h = Output Disabled 1h = Output Enabled
6	Output Enable, CK6	R/W	1h	This bit controls the output enable signal for output channel CK6_P/CK6_N. 0h = Output Disabled 1h = Output Enabled
5	Output Enable, CK5	R/W	1h	This bit controls the output enable signal for output channel CK5_P/CK5_N. 0h = Output Disabled 1h = Output Enabled
4	Output Enable, CK4	R/W	1h	This bit controls the output enable signal for output channel CK4_P/CK4_N. 0h = Output Disabled 1h = Output Enabled
3	Output Enable, CK3	R/W	1h	This bit controls the output enable signal for output channel CK3_P/CK3_N. 0h = Output Disabled 1h = Output Enabled
2	Output Enable, CK2	R/W	1h	This bit controls the output enable signal for output channel CK2_P/CK2_N. 0h = Output Disabled 1h = Output Enabled
1	Output Enable, CK1	R/W	1h	This bit controls the output enable signal for output channel CK1_P/CK1_N. 0h = Output Disabled 1h = Output Enabled
0	Output Enable, CK0	R/W	1h	This bit controls the output enable signal for output channel CK0_P/CK0_N. 0h = Output Disabled 1h = Output Enabled

7.1.3 OECR3 Register (Address = 2h) [reset = FFh]

OECR3 is shown in Table 7-5.

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The OECR3 register contains bits that enable or disable individual output clock channels [15:8]

Table 7-5 OECR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	Output Enable, CK15	R/W	1h	This bit controls the output enable signal for output channel CK15_P/CK15_N. 0h = Output Disabled 1h = Output Enabled
6	Output Enable, CK14	R/W	1h	This bit controls the output enable signal for output channel CK14_P/CK14_N. 0h = Output Disabled 1h = Output Enabled
5	Output Enable, CK13	R/W	1h	This bit controls the output enable signal for output channel CK13_P/CK13_N. 0h = Output Disabled 1h = Output Enabled
4	Output Enable, CK12	R/W	1h	This bit controls the output enable signal for output channel CK12_P/CK12_N. 0h = Output Disabled 1h = Output Enabled
3	Output Enable, CK11	R/W	1h	This bit controls the output enable signal for output channel CK11_P/CK11_N. 0h = Output Disabled 1h = Output Enabled
2	Output Enable, CK10	R/W	1h	This bit controls the output enable signal for output channel CK10_P/CK10_N. 0h = Output Disabled 1h = Output Enabled
1	Output Enable, CK9	R/W	1h	This bit controls the output enable signal for output channel CK9_P/CK9_N. 0h = Output Disabled 1h = Output Enabled
0	Output Enable, CK8	R/W	1h	This bit controls the output enable signal for output channel CK8_P/CK8_N. 0h = Output Disabled 1h = Output Enabled

7.1.4 OERDBK Register (Address = 3h) [reset = 0h]

OERDBK is shown in Table 7-6.

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The OERDBK register contains bits that report the current state of the OE[12:5]# input pins.

Table 7-6 OERDBK Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE12# State	R	0h	This bit reports the logic level present on the OE12# pin.
6	OE11# State	R	0h	This bit reports the logic level present on the OE11# pin.
5	OE10# State	R	0h	This bit reports the logic level present on the OE10# pin.
4	OE9# State	R	0h	This bit reports the logic level present on the OE9# pin.
3	OE8# State	R	0h	This bit reports the logic level present on the OE8# pin.
2	OE7# State	R	0h	This bit reports the logic level present on the OE7# pin.
1	OE6# State	R	0h	This bit reports the logic level present on the OE6# pin.
0	OE5# State	R	0h	This bit reports the logic level present on the OE5# pin.

7.1.5 SBRDBK Register (Address = 4h) [reset = 1h]

SBRDBK is shown in Table 7-7.

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The SBRDBK register contains a bit that report the current state of the SBEN input pin.

Table 7-7 SBRDBK Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0h	Reserved
0	SBEN State	R/W	1h	This bit reports the logic level present on the SBEN pin.

7.1.6 VDRREVID Register (Address = 5h) [reset = X]

VDRREVID is shown in Table 7-8.

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The VDRREVID register contains a vendor identification code and silicon revision code.

Table 7-8 VDRREVID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Revision Code[3:0]	R	X	Silicon revision code. Silicon revision code bits [3:0] map to register bits [7:4] directly.
3-0	Vendor ID[3:0]	R	X	Vendor identification code. Vendor ID bits [3:0] map to register bits [3:0] directly.

7.1.7 DEVID Register (Address = 6h) [reset = X]

DEVID is shown in Table 7-9.

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The DEVID register contains a device identification code.

Table 7-9 DEVID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Device ID[7:0]	R	X	Device ID code. Device ID bits[7:0] map to register bits[7:0] directly.

7.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]

BTRDCNT is shown in Table 7-10.

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The BTRDCNT register allows configuration of the number of bytes that is read back from the SMBus interface on an issued read command.

Table 7-10 BTRDCNT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	Reserved
5-0	Read Byte Count[5:0]	R/W	8h	Writing to this register configures how many bytes is read back.

7.1.9 SBIMSK1 Register (Address = 8h) [reset = 0h]

SBIMSK1 is shown in Table 7-11.

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The SBIMSK1 register allows the SMBus to force enable each output channel individually when the CDCDB2000 is in Side-Band interface mode.

Table 7-11 SBIMSK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SBI Output Mask, CK7	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK7 Enabled
6	SBI Output Mask, CK6	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK6 Enabled
5	SBI Output Mask, CK5	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK5 Enabled
4	SBI Output Mask, CK4	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK4 Enabled
3	SBI Output Mask, CK3	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK3 Enabled
2	SBI Output Mask, CK2	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK2 Enabled
1	SBI Output Mask, CK1	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK1 Enabled
0	SBI Output Mask, CK0	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK0 Enabled

7.1.10 SBIMSK2 Register (Address = 9h) [reset = 0h]

SBIMSK2 is shown in Table 7-12.

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The SBIMSK2 register allows the SMBus to force enable each output channel individually when the CDCDB2000 is in Side-Band interface mode.

Table 7-12 SBIMSK2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SBI Output Mask, CK15	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK15 Enabled
6	SBI Output Mask, CK14	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK14 Enabled
5	SBI Output Mask, CK13	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK13 Enabled
4	SBI Output Mask, CK12	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK12 Enabled
3	SBI Output Mask, CK11	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK11 Enabled
2	SBI Output Mask, CK10	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK10 Enabled
1	SBI Output Mask, CK9	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK9 Enabled
0	SBI Output Mask, CK8	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK8 Enabled

7.1.11 SBIMSK3 Register (Address = Ah) [reset = 0h]

SBIMSK3 is shown in Table 7-13.

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The SBIMSK3 register allows the SMBus to force enable each output channel individually when the CDCDB2000 is in Side-Band interface mode.

Table 7-13 SBIMSK3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	SBI Output Mask, CK19	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK19 Enabled
2	SBI Output Mask, CK18	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK18 Enabled
1	SBI Output Mask, CK17	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK17 Enabled
0	SBI Output Mask, CK16	R/W	0h	This bit overrides the SBI output disable when set. 0h = SBI Controls Output 1h = Output CK16 Enabled

7.1 CDCDB2000 Registers

7.1.1 OECR1 Register (Address = 0h) [reset = 78h]

7.1.2 OECR2 Register (Address = 1h) [reset = FFh]

7.1.3 OECR3 Register (Address = 2h) [reset = FFh]

7.1.4 OERDBK Register (Address = 3h) [reset = 0h]

7.1.5 SBRDBK Register (Address = 4h) [reset = 1h]

7.1.6 VDRREVID Register (Address = 5h) [reset = X]

7.1.7 DEVID Register (Address = 6h) [reset = X]

7.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]

7.1.9 SBIMSK1 Register (Address = 8h) [reset = 0h]

7.1.10 SBIMSK2 Register (Address = 9h) [reset = 0h]

7.1.11 SBIMSK3 Register (Address = Ah) [reset = 0h]