DB2000QL compliant 20-output clock buffer for PCIe Gen 1 to Gen 5


Product details


Function Differential Additive RMS jitter (Typ) (fs) 80 Output frequency (Max) (MHz) 250 Number of outputs 20 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features 1:20 fanout, PCIe Gen 1-5 compliance, DB2000QL compliant, SMBus control, Side-Band Interface, OE# control Operating temperature range (C) -40 to 85 Rating Catalog Output type LP-HCSL Input type LP-HCSL open-in-new Find other Clock buffers

Package | Pins | Size

TLGA (NPP) 80 36 mm² 6 x 6 open-in-new Find other Clock buffers


  • 20 LP-HCSL outputs with integrated 85-Ω output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after DB2000QL filter:
    < 0.08ps rms
  • Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Cycle-to-cycle jitter: < 50 ps
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns
  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Side-Band Interface (SBI) for output control in PD# mode
  • 9 selectable SMBus addresses
  • Power consumption: < 600 mW
  • 6-mm × 6-mm, 80-pin TLGA/GQFN package

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The CDCDB2000 is a 20-output LP-HCSL, DB2000QL compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus, SBI, and 8 output enable pins allow the configuration and control of all 20 outputs individually. The CDCDB2000 is a DB2000QL derivative buffer and meets or exceeds the system parameters in the DB2000QL specification. The CDCDB2000 is packaged in a 6-mm × 6-mm TLGA/GQFN package with 80 leads.

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Technical documentation

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* Data sheet CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5 datasheet (Rev. A) Feb. 19, 2020
User guide CDCDB2000 User's Guide Oct. 29, 2019

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SNAM232.ZIP (30 KB) - IBIS Model
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TLGA (NPP) 80 View options

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