Home Clocks & timing Clock buffers
Home
Clocks & timing
Clock buffers

CDCDB2000

ACTIVE

DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 5

Order now
Data sheet

CDCDB2000

ACTIVE
Data sheet Order now

Product details

Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 80 Output frequency (max) (MHz) 250 Number of outputs 20 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features 1:20 fanout, DB2000QL compliant, Individual output enable control, OE# control, PCIe Gen 1-5 compliant, SMBus control, Side-Band Interface Operating temperature range (°C) -40 to 85 Rating Catalog Output type LP-HCSL Input type LP-HCSL
Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 80 Output frequency (max) (MHz) 250 Number of outputs 20 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features 1:20 fanout, DB2000QL compliant, Individual output enable control, OE# control, PCIe Gen 1-5 compliant, SMBus control, Side-Band Interface Operating temperature range (°C) -40 to 85 Rating Catalog Output type LP-HCSL Input type LP-HCSL
TLGA (NPP) 80 36 mm² 6 x 6
  • 20 LP-HCSL outputs with integrated 85-Ω output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after DB2000QL filter:
    < 0.08ps rms
  • Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Cycle-to-cycle jitter: < 50 ps
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns
  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Side-Band Interface (SBI) for output control in PD# mode
  • 9 selectable SMBus addresses
  • Power consumption: < 600 mW
  • 6-mm × 6-mm, 80-pin TLGA/GQFN package
  • 20 LP-HCSL outputs with integrated 85-Ω output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after DB2000QL filter:
    < 0.08ps rms
  • Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Cycle-to-cycle jitter: < 50 ps
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns
  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Side-Band Interface (SBI) for output control in PD# mode
  • 9 selectable SMBus addresses
  • Power consumption: < 600 mW
  • 6-mm × 6-mm, 80-pin TLGA/GQFN package

The CDCDB2000 is a 20-output LP-HCSL, DB2000QL compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus, SBI, and 8 output enable pins allow the configuration and control of all 20 outputs individually. The CDCDB2000 is a DB2000QL derivative buffer and meets or exceeds the system parameters in the DB2000QL specification. The CDCDB2000 is packaged in a 6-mm × 6-mm TLGA/GQFN package with 80 leads.

The CDCDB2000 is a 20-output LP-HCSL, DB2000QL compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus, SBI, and 8 output enable pins allow the configuration and control of all 20 outputs individually. The CDCDB2000 is a DB2000QL derivative buffer and meets or exceeds the system parameters in the DB2000QL specification. The CDCDB2000 is packaged in a 6-mm × 6-mm TLGA/GQFN package with 80 leads.
open-in-new Find other Clock buffers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Same functionality with different pin-out to the compared device
CDCDB800 ACTIVE 8-output clock buffer for PCIe® Gen 1 to Gen 6 DB800ZL compliant with output enable/disable

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5 datasheet (Rev. A) PDF | HTML 19 Feb 2020
User guide CDCDB2000 User's Guide 29 Oct 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

CDCDB2000 IBIS Model (Rev. A)

SNAM232A.ZIP (30 KB) - IBIS Model
Download
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Gerber file

CDCDB2000 Board Files

SNAC085.ZIP (11498 KB)
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins Download
TLGA (NPP) 80 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos