SNAS787C November   2019  – August 2025 CDCDB2000

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable Control
      2. 6.3.2 SMBus
        1. 6.3.2.1 SMBus Address Assignment
      3. 6.3.3 Side-Band Interface
    4. 6.4 Device Functional Modes
      1. 6.4.1 CKPWRGD_PD# Function
      2. 6.4.2 OE[12:5]# and SMBus Output Enables
    5. 6.5 Programming
      1. 6.5.1 SMBus
      2. 6.5.2 SBI
  8. 7 Register Maps
    1. 7.1 CDCDB2000 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Enable Control Method
        2. 8.2.2.2 SMBus Address
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 TICS Pro
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.4.2 OE[12:5]# and SMBus Output Enables

Each output channel, 0 to 19, can be individually enabled or disabled by SMBus control register bits, called SMB enable bits. Additionally, each output channel from 12 to 5 has a dedicated, corresponding, OE[12:5]# hardware pin. The OE[12:5]# pins are asynchronously asserted-low signals that can enable or disable the output.

Refer to Table 6-2 for enabling and disabling outputs through the hardware and software. Note that both the SMB enable bit must be a ‘1’ and the OEx# pin must be an input low voltage ‘0’ for the output channel to be active.

Table 6-2 is only valid when the SBEN signal is low (SBEN = 0).

Table 6-2 OE[12:5]# Functionality When SBEN = 0
INPUTSOE[12:5]# HARDWARE PINS AND SMBus CONTROL REGISTER BITS
PWRGDPD#CLKINSMBus ENABLE BIT (byte[2:0])OE[12:5]#CK[12:5]CK[19:13, 4:0]
0XXXXLOWLOW
10XXXTristateTristate
11Running0X00
11Running10RunningRunning
11Running110Running