SNAS787C November   2019  – August 2025 CDCDB2000

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable Control
      2. 6.3.2 SMBus
        1. 6.3.2.1 SMBus Address Assignment
      3. 6.3.3 Side-Band Interface
    4. 6.4 Device Functional Modes
      1. 6.4.1 CKPWRGD_PD# Function
      2. 6.4.2 OE[12:5]# and SMBus Output Enables
    5. 6.5 Programming
      1. 6.5.1 SMBus
      2. 6.5.2 SBI
  8. 7 Register Maps
    1. 7.1 CDCDB2000 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Enable Control Method
        2. 8.2.2.2 SMBus Address
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 TICS Pro
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

VDD, VDD_A = 3.3V ±5 %, -40°C< TA < 85°C. Typical values are at VDD = VDD_A = 3.3V, 25°C(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
IDD_A Core supply current Active mode. CKPWRGD_PD# = 1 12 mA
Power down mode. CKPWRGD_PD# = 0 8
IDD IO supply current per output All-outputs disabled 20 mA
All-outputs active, 100MHz 200
Power down mode. CKPWRGD_PD# = 0 8
CLOCK INPUT
fIN Input frequency 50 100 250 MHz
VIN Input voltage swing Differential voltage between CLKIN_P and CLKIN_N(1) 200 2300 mVDiff-peak
dV/dt Input voltage edge rate 20% - 80% of input swing 0.7 V/ns
DVCROSS Total variation of VCROSS Total variation across VCROSS 140 mV
DCIN Input duty cycle 40 60 %
CIN Input capacitance(2) Differential capacitance between CLKIN_P and CLKIN_N pins 2.2 pF
CLOCK OUTPUT
fOUT Output frequency 50 100 250 MHz
COUT Output capacitance(1) Differential capacitance between CKx_P and CKx_N pins 2.2 pF
VOH Output high voltage Single-ended(2)(3) 225 270 mV
VOL Output low voltage 10 150
VCROSS Crossing point voltage Input VCROSS varied by 140mV. (3)(4) 130 200
DVCROSS Total variation of VCROSS Input VCROSS varied by 140mV. Variation of VCROSS(3)(4) 35
Vovs Overshoot voltage (3) VOH+75
Vuds Undershoot voltage (3) VOL–75
ZDIFF Differential impedance Measured at VOL/VOH 81 85 89 Ω
ZDIFF_CROSS Differential impedance Measured at VCROSS 68 85 102
tEDGE Edge rate Measured at VCROSS 2 20 V/ns
DtEDGE Edge rate matching Measured at VCROSS 20 %
tSTABLE Power good assertion to stable clock output CKPWRGD_PD# pin transitions from 0 to 1, fIN = 100MHz Measured when PWRGD reaches 0.2V 1.8 ms
tDRIVE_PD# Power good assertion to outputs driven high CKPWRGD_PD# pin transitions from 0 to 1, fIN = 100MHz Measured when PWRGD reaches 0.2V 300 µs
tOE Output enable assertion to stable clock output OEx# pin transitions from 1 to 0 10 CLKIN Periods
tOD Output enable de-assertion to no clock output OEx# pin transitions from 0 to 1 10
tPD Power down assertion to no clock output CKPWRGD_PD# pin transitions from 1 to 0 3
tDCD Duty cycle distortion Differential; fIN = 100MHz, fin_DC = 50% –1.0 1.0 %
tDLY Propagation delay (5) 0.5 3 ns
tSKEW Skew between outputs (6) 50 ps
JCKx_PCIE Additive jitter DB2000QL filter 0.08 ps, rms

Additive jitter for PCIe7

PCIe7.0 filter

11.3

fs, rms

Additive jitter for PCIe6

PCIe6.0 filter

16.1

fs, rms
Additive jitter for PCIe5 PCIe5.0 filter

26.4

 fs, rms
Additive jitter for PCIe4 PLL BW = 2 to 5MHz; CDR = 10MHz Input clock slew rate ≥ 1.8V/ns 0.08 ps, rms
Additive jitter for PCIe3 Input clock slew rate ≥ 0.6V/ns 0.15 ps, rms
JCKx_PCIE Additive jitter for PCIe2 PCIe2 filter 0.2 ps, rms
JCKx_PCIE Additive jitter for PCIe1 PCIe1 filter 5 ps, rms
JCKx Additive jitter fIN = 100MHz; slew rate ≥ 3V/ns; 12kHz to 20MHz integration bandwidth. 155 fs, rms
SMBUS INTERFACE, SIDE-BAND INTERFACE, OEx#, CKPWRGD_PD#, SBEN
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8
IIL Input leakage current With internal pull up/pull-down GND < VIN < VDD –30 30 µA
Without internal pull up/pull-down –5 5
CIN Input capacitance 4.5 pF
COUT Output capacitance 4.5 pF
3-LEVEL DIGITAL INTERFACE (SA_0, SA_1)
VIHT High-level input voltage 2.4 V
VIMT Mid level input voltage 1.3 VDD/2 1.8
VILT Low-level input voltage 0.9
IINT Input high current VIN = VDD, VIN = GND -10 10 µA
ILeak Input leakage current With internal pull up/pull-down GND < VIN < VDD –30 30
(1) Voltage swing includes overshoot.
(2) Not tested in production. Verified by design and characterization.
(3) Measured into DC test load.
(4) VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P is rising.
(5) Measured from rising edge of CLK_IN to any CKx output.
(6) Measured from rising edge of any CKx output to any other CKx output.