SNAS862B April   2025  – October 2025 LMK3H0102-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
    2. 6.2 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA0]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3066]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x4000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0x6800]
      14. 8.1.14 R146 Register (Address = 0x92) [reset = 0x0000]
      15. 8.1.15 R147 Register (Address = 0x93) [reset = 0x0000]
      16. 8.1.16 R148 Register (Address = 0x94) [reset = 0x0000]
      17. 8.1.17 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Example: Changing Output Frequency
        2. 9.2.3.2 Crosstalk
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

LMK3H0102-Q1 LMK3H0102-Q1 16-Pin VQFN Top View Figure 4-1 LMK3H0102-Q1 16-Pin VQFN Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
OUT0_P, 8 O Clock output 0. Supports LP-HCSL (85Ω or 100Ω), LVDS or 1.8V/2.5V/3.3V LVCMOS.
OUT0_N 7
OUT1_P 12 O Clock output 1. Supports LP-HCSL (85Ω or 100Ω), LVDS or 1.8V/2.5V/3.3V LVCMOS.
OUT1_N 11
REF_CTRL (REF_CLK) 15 I/O

Multifunctional pin. At power up, the state of this pin is latched to select the functionality of Pin 2, Pin 3 and Pin 4. Pull low or leave floating for I2C mode or high for OTP mode prior to power-up. After power-up, this pin can be programmed as an additional LVCMOS output (REF_CLK), active-high CLK_READY signal, or disabled.

See REF_CTRL Operation for more details.

This pin has an 880kΩ internal pulldown resistor.

OE 1 I

Output Enable. Active low. 2-state logic input pin.

This pin has a 75kΩ internal pulldown resistor.

This pin can control either OUT0 alone or OUT0 and OUT1. See Output Enable for more details.

  • Low/Floating: OUT0 and OUT1 enabled
  • High: OUT0 and OUT1 disabled
FMT_ADDR 2 I

Multifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power up. See OTP Mode and I2C Mode for more details.

This pin has an 880kΩ internal pulldown resistor.

  • I2C Mode: This pin can select the I2C address, function as the output enable for OUT1, or have no function.
  • OTP Mode: This pin can set the output format, function as the output enable for OUT1, or have no function.
OTP_SEL0/SCL 3 I, I/O Multifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power up. See OTP Mode and I2C Mode for details.
  • I2C Mode: These pins are the I2C clock and data connections.
  • OTP Mode: These pins select the OTP page.
OTP_SEL1/SDA 4
VDD 5, 14, 16 P 1.8V, 2.5V or 3.3V device power supply. A 0.1µF capacitor must be placed as close to each of the pins as possible. For LMK3H0102T18, only provide 1.8V to this pin.
VDDO_0 10, 13 P

1.8V, 2.5V or 3.3V OUT0 and OUT1 power supply. If VDD is 1.8V or 2.5V, the VDDO pins must be the same voltage as VDD. A 0.1µF capacitor must be placed as close to each of the pins as possible. When using split power supply, see Power-Up Sequencing for proper implementation.
VDDO_1 13
GND 6, 9 G Electrical GND. These pins MUST be connected to GND for the device to function.
DAP 17 G Thermal GND. The DAP is NOT connected to electrical GND inside the device, and is used for thermal GND only. Connect to an inner GND layer with multiple vias.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.