SNAS862B April   2025  – October 2025 LMK3H0102-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
    2. 6.2 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA0]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3066]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x4000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0x6800]
      14. 8.1.14 R146 Register (Address = 0x92) [reset = 0x0000]
      15. 8.1.15 R147 Register (Address = 0x93) [reset = 0x0000]
      16. 8.1.16 R148 Register (Address = 0x94) [reset = 0x0000]
      17. 8.1.17 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Example: Changing Output Frequency
        2. 9.2.3.2 Crosstalk
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

VDD = VDDO = 1.8V, 2.5V or 3.3V ± 5%, TA = TA,min to TA,max
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY STABILITY
∆ftotal Total frequency stability All factors included: temperature variation, 10-year aging at 25℃, solder shift, hysteresis and initial frequency accuracy –25 25 ppm
LP-HCSL CLOCK OUTPUT CHARACTERISTICS
fout Output frequency 2.5 400 MHz
Vmin Output low voltage (undershoot included) –60 25 mV
Vovershoot Overshoot voltage. Vmax - VOH 150 mV
VOH,2.5/3.3 Output high voltage. VDD = 2.5V or 3.3V code = 0 563 625 688 mV
code = 1 582 647 712 mV
code = 2 601 668 735 mV
code = 3 621 690 759 mV
code = 4 641 712 783 mV
code = 5 660 733 806 mV
code = 6 (default) 680 755 831 mV
code = 7 699 777 855 mV
code = 8 718 798 878 mV
code = 9 738 820 902 mV
code = 10 758 842 926 mV
code = 11 777 863 949 mV
code = 12 797 885 974 mV
code = 13 816 907 998 mV
code = 14 835 928 1021 mV
code = 15 855 950 1045 mV
VOH,1.8 Output high voltage. VDD = 1.8V code = 0 563 625 688 mV
code = 1 582 647 712 mV
code = 2 601 668 735 mV
code = 3 621 690 759 mV
code = 4 641 712 783 mV
code = 5 660 733 806 mV
code = 6 (default) 680 755 831 mV
code = 7 699 777 855 mV
code = 8 718 798 878 mV
code = 9 738 820 902 mV
code = 10 758 842 926 mV
code = 11 777 863 949 mV
code = 12 797 885 974 mV
code = 13 816 907 998 mV
code = 14 835 928 1021 mV
code = 15 855 950 1045 mV
Zdiff LP-HCSL static differential impedance 80.75 85 91.25 Ω
95 100 105 Ω
dV/dt Output slew rate (rising and falling edge) Measured from –150mV to +150mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 0(1) 2.1 3.1 V/ns
Measured from –150mV to +150mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 0 2.3 3.5 V/ns
Measured from –150mV to +150mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 1 2 3.2 V/ns
Measured from –150mV to +150mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 2 1.7 2.8 V/ns
Measured from –150mV to +150mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 3 1.4 2.7 V/ns
∆dV/dt Rising edge rate to falling edge rate matching See(1) 3 %
ODC Output duty cycle See(1) 47 53 %
fout ≤ 325MHz 47 53 %
325MHz < fout ≤ 400MHz 47 53 %
tskew Output to output skew Same FOD, LP-HCSL output 50 ps
Vcross Absolute crossing point voltage See(1) 280 480 mV
∆Vcross Variation of Vcross over all clock edges See(1) 30 mV
|VRB| Absolute value of ring back voltage See(1) 100 mV
tstable Time before VRB is allowed See(1) 500 ps
Jcycle-to-cycle Cycle to cycle jitter, Common Clock no SSC See(1) 20 ps
Jcycle-to-cycle Cycle to cycle jitter, Common Clock, –0.5% SSC See(1) 25 ps
tperiod_abs Absolute period including jitter and SSC See(1) 9.949 10 10.101 ns
tperiod_avg_CC Average clock period accuracy, Common Clock See(1) –100 2600 ppm
tperiod_avg_SRIS Average clock period accuracy, SRIS See(1) –100 1600 ppm
LVDS CLOCK OUTPUT CHARACTERISTICS
fout Output frequency 2.5 400 MHz
|VOD| Steady-state magnitude of the differential output voltage |VOUTP - VOUTN| 100Ω external termination 250 350 450 mV
∆Vpp-diff Change in differential output voltage swing between complementary output states 100Ω external termination 50 mV
VOS Output offset voltage (common mode voltage) VDDO = 3.3V, 100Ω external termination 1.12 1.2 1.365 V
VDDO = 2.5V, 100Ω external termination 1.1 1.2 1.345 V
VDDO = 1.8V, 100Ω external termination 0.8 0.97 V
∆VOS Change in VOS between complementary output states 50 mV
ISA, ISB Short-circuit current. Magnitude of current with the generator output terminals short-circuited to the generator circuit common –24 24 mA
ISAB Short-circuit current. Magnitude of current with generator output terminals short-circuited to each other –12 12 mA
tR, tF 20% to 80% differential rise/fall time OUTx_SLEW_RATE = 0 195 323 ps
OUTx_SLEW_RATE = 1 250 454 ps
OUTx_SLEW_RATE = 2 270 635 ps
OUTx_SLEW_RATE = 3 280 792 ps
tskew Output to output skew Same FOD, LVDS output 50 ps
ODC Output duty cycle 47 53 %
LVCMOS CLOCK OUTPUT CHARACTERISTICS
fout Output frequency 2.5 200 MHz
dV/dt Output slew rate VDDO = 3.3V ± 5%, measured from 20% to 80%, 4.7pF load 2.6 4.7 V/ns
VDDO = 2.5V ± 5%, measured from 20% to 80%, 4.7pF load 2.6 3.7 V/ns
VDDO = 1.8V ± 5%, measured from 20% to 80%, 4.7pF load 1.5 3.2 V/ns
VOH Output high voltage IOH = –15mA at 3.3V 0.8 × VDDO VDDO V
IOH = –12mA at 2.5V
IOH = –8mA at 1.8V
VOL Output low voltage IOL = 15mA at 3.3V 0.4 V
IOL = 12mA at 2.5V
IOL = 8mA at 1.8V
Ileak Output leakage current Output tri-stated. VDD = VDDO = 3.465V –5 0 5 µA
Rout Output impedance 17 Ω
ODC Output duty cycle fout ≤ 156.25MHz 45 55 %
fout > 156.25MHz 40 60 %
tskew Output-to-output skew Same FOD, LVCMOS output 50 ps
Cload Maximum load capacitance 15 pF
LVCMOS REFCLK CHARATERISTICS
fout Output frequency See(2) 12.5(3) 200 MHz
dV/dt Output slew rate VDDO = 3.3V ± 5%, measured from 20% to 80%, 4.7pF load(2) 2.6 6.7 V/ns
VDDO = 2.5V ± 5%, measured from 20% to 80%, 4.7pF load(2) 1.8 4.5 V/ns
VDDO = 1.8V ± 5%, measured from 20% to 80%, 4.7pF load(2) 1 3.2 V/ns
Ileak Output leakage current Output in tri-state condition. VDD = VDDO = 3.465V(2) –5 5 µA
Rout Output impedance 17 Ω
ODC Output duty cycle fout ≤ 156.25MHz(2) 45 55 %
ODC Output duty cycle fout > 156.25MHz(2) 40 60 %
Cload Maximum load capacitance See(2) 15 pF
RJ Random jitter 12kHz to 20MHz integrated jitter at 50MHz(2) 0.5 ps
SSC CHARACTERISTICS
fout Output frequency range that supports SSC (any output format) 2.5 200 MHz
fSSC SSC modulation frequency 30 31.5 33 kHz
fSSC-deviation SSC deviation (modulation depth) Down spread (programmable) –3 –0.1 %
Center spread (programmable) ±0.05 ±1.5 %
fSSC-deviation-accuracy SSC deviation accuracy fout ≤ 100MHz, down spread 0 0.01 %
100MHz < fout ≤ 200MHz, down spread 0 0.05 %
fout ≤ 100MHz, center spread 0 0.01 %
100MHz < fout ≤ 200MHz, center spread 0 0.05 %
df/dt max SSC frequency slew rate 0 < fSSC-deviation ≤ –0.5% 1250 ppm/µs
JITTER CHARACTERISTICS
JPCIe1-cc-SSC_off PCIe Gen 1 Common Clock jitter, SSC is off (jitter limit = 86ps) SSC disabled on both outputs 0.8 ps
JPCIe1-cc-SSC_on PCIe Gen 1 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 86ps) SSC enabled on both outputs 1.4 ps
JPCIe2-cc-SSC_off PCIe Gen 2 Common Clock jitter, SSC is off (jitter limit = 3ps) SSC disabled on both outputs 0.2 0.3 ps
JPCIe2-cc-SSC_on PCIe Gen 2 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 3ps) SSC enabled on both outputs 0.3 0.5 ps
JPCIe2-SRNS PCIe Gen 2 SRNS jitter SSC disabled on both outputs 0.2 0.3 ps
JPCIe2-SRIS PCIe Gen 2 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 0.3 0.5 ps
JPCIe3-cc-SSC_off PCIe Gen 3 Common Clock jitter, SSC is off (jitter limit = 1ps) SSC disabled on both outputs 42.8 84.2 fs
JPCIe3-cc-SSC_on PCIe Gen 3 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 1ps) SSC enabled on both outputs 63.1 135.3 fs
JPCIe3-SRNS PCIe Gen 3 SRNS jitter SSC disabled on both outputs 48.8 97.5 fs
JPCIe3-SRIS PCIe Gen 3 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 194.1 418.5 fs
JPCIe4-cc-SSC_off PCIe Gen 4 Common Clock jitter, SSC is off (jitter limit = 500fs) SSC disabled on both outputs 42.8 84.2 fs
JPCIe4-cc-SSC_on PCIe Gen 4 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 500fs) SSC enabled on both outputs 63.1 135.3 fs
JPCIe4-SRNS PCIe Gen 4 SRNS jitter SSC disabled on both outputs 48.8 97.5 fs
JPCIe4-SRIS PCIe Gen 4 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 98.5 205.4 fs
JPCIe5-cc-SSC_off PCIe Gen 5 Common Clock jitter, SSC is off (jitter limit = 150fs) SSC disabled on both outputs 17.8 35.6 fs
JPCIe5-cc-SSC_on PCIe Gen 5 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 150fs) SSC enabled on both outputs 26.4 57.5 fs
JPCIe5-SRNS PCIe Gen 5 SRNS jitter SSC disabled on both outputs 19.8 39 fs
JPCIe5-SRIS PCIe Gen 5 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 30.2 63.9 fs
JPCIe6-cc-SSC_off PCIe Gen 6 Common Clock jitter, SSC is off (jitter limit = 100fs) SSC disabled on both outputs 11 22 fs
JPCIe6-cc-SSC_on PCIe Gen 6 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 100fs) SSC enabled on both outputs 16 34.5 fs
JPCIe6-SRNS PCIe Gen 6 SRNS jitter SSC disabled on both outputs 14.8 27.9 fs
JPCIe6-SRIS PCIe Gen 6 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 22.2 45.9 fs
JPCIe7-cc-SSC_off PCIe Gen 7 Common Clock jitter, SSC is off (jitter limit = 67fs) SSC disabled on both outputs 7.7 15.4 fs
JPCIe7-cc-SSC_on PCIe Gen 7 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 67fs) SSC enabled on both outputs 12.1 29.6 fs
JPCIe7-SRNS PCIe Gen 7 SRNS jitter SSC disabled on both outputs 10.4 19.6 fs
JPCIe7-SRIS PCIe Gen 7 SRIS jitter, –0.1% ≤ SSC < 0% SSC enabled on both outputs 12.2 25.5 fs
RJRMS 12kHz to 20MHz RMS jitter fout = 156.25MHz 105 144 fs
TIMING CHARACTERISTICS
tstartup Start-up time VDD = 2.5V or 3.3V. Time elapsed from all VDD pins reach 2.1V until first output clock rising edge. Output clock is always within specification 1 ms
VDD = 1.8V. Time elapsed from all VDD pins reach 1.6V until first output clock rising edge. Output clock is always within specification 1.5 ms
tOE Output enable time.  After CLOCK_READY status is '1', time elapsed between OE assertion and first output clock rising edge. Output is not tristated when disabled. 7 output clock cycles
tOD Output disable time.  Time elapsed between OE deassertion and last output clock falling edge. 7 output clock cycles
POWER CONSUMPTION CHARACTERISTICS
IDD Core supply current, not including output drivers One FOD enabled, 100MHz ≤ fFOD ≤ 200MHz 57.5 79.9 mA
One FOD enabled, 200MHz < fFOD ≤ 400MHz 67 90.7 mA
Two FODs enabled, 100MHz ≤ fFOD ≤ 200MHz 81.1 105.8 mA
Two FODs enabled, 200MHz < fFOD ≤ 400MHz 97.8 125.8 mA
IDDO Output supply current, per output channel LP-HCSL. fout ≤ 100MHz 10.1 10.8 mA
LP-HCSL. 100MHz < fout ≤ 200MHz 13.2 14.1 mA
LP-HCSL. 200MHz < fout ≤ 300MHz 13.7 15.1 mA
LP-HCSL. 300MHz < fout ≤ 400MHz 14.4 16.4 mA
LVDS. fout ≤ 100MHz 6 8 mA
LVDS. 100MHz < fout ≤ 200MHz 6.8 9.2 mA
LVDS. 200MHz < fout ≤ 300MHz 7.6 10.2 mA
LVDS. 300MHz < fout ≤ 400MHz 8.4 11.3 mA
1.8V LVCMOS. fout = 50MHz(4) 4.2 5 mA
1.8V LVCMOS. fout = 200MHz(4) 11.7 13.4 mA
2.5V LVCMOS. fout = 50MHz(4) 5.6 6.4 mA
2.5V LVCMOS. fout = 200MHz(4) 15.3 17.3 mA
3.3 VLVCMOS. fout = 50MHz(4) 6.8 7.7 mA
3.3V LVCMOS. fout = 200MHz(4) 19.2 21.7 mA
IDDREF REFCLK supply current 1.8V LVCMOS. fout = 50MHz(4) 3.4 3.9 mA
1.8V LVCMOS. fout = 200MHz(4) 9.5 11.7 mA
2.5V LVCMOS. fout = 50MHz(4) 4.7 5.3 mA
2.5V LVCMOS. fout = 200MHz(4) 12.8 15.8 mA
3.3V LVCMOS. fout = 50MHz(4) 5.9 6.6 mA
3.3V LVCMOS. fout = 200MHz(4) 16.6 20.2 mA
PSNR CHARACTERISTICS
PSNRLVCMOS Power Supply Noise Rejection for LVCMOS outputs(5) 10kHz –76.7 -58.1 dBc
50kHz –80.9 -57.9 dBc
100kHz –81.8 -57 dBc
500kHz –84.3 -61.7 dBc
1MHz –97.6 -78.1 dBc
5MHz –104.3 -79 dBc
10MHz –108.7 -89.5 dBc
PSNRLVDS Power Supply Noise Rejection for LVDS outputs(5) 10kHz –79.5 -70.9 dBc
50kHz –83.5 -73.2 dBc
100kHz –83 -71.6 dBc
500kHz –88.3 -79 dBc
1MHz –123.4 -101.4 dBc
5MHz –115 -87.7 dBc
10MHz –123.7 -103.5 dBc
PSNRLP-HCSL Power Supply Noise Rejection for LP-HCSL outputs(5) 10kHz –80.1 -70.8 dBc
50kHz –84.7 -72.9 dBc
100kHz –84.6 -70.1 dBc
500kHz –93.1 -78.8 dBc
1MHz –124.6 -101.5 dBc
5MHz –114.3 -88.3 dBc
10MHz –123 -103.7 dBc
2-STATE LOGIC INPUT CHARACTERISTICS
VIH-Pin2 Input high voltage for Pin 2 0.7 × VDD VDD + 0.3 V
VIL-Pin2 Input low voltage for Pin 2 GND – 0.3 0.3 × VDD V
VIH-Pin1 Input high voltage for Pin 1 1.15 VDD + 0.3 V
VIL-Pin1 Input low voltage for Pin 1 –0.3 0.65 V
VIH-Pin3,4 Input voltage high for OTP_SEL[1:0] 0.7 × VDD VDD + 0.3 V
VIL-Pin3,4 Input voltage low for OTP_SEL[1:0] GND - 0.3 0.8 V
VIH-Pin15 Input voltage high for Pin 15 0.65 × VDD VDD + 0.3 V
VIL-Pin15 Input voltage low for Pin 15 –0.3 0.4 V
Rext-up/down-Pin1,2 Recommended external pullup or pulldown resistor for Pin 1, 2 0 1 10 kΩ
Rext-up/down-Pin3,4,15 Recommended external pullup or pulldown resistor for Pin 3, 4, 15 0 10 60 kΩ
tR/tF OE signal rise or fall time 10 ns
Cin Input capacitance 3 pF
(1) PCIe test load, 15dB loss at 4GHz, fout = 100MHz, Zdiff = 100Ω
(2) Tested with 10kΩ external pullup or pulldown resistor
(3) REFCLK can be /2, /4, /8 from either FOD0 or FOD1. Both FODs support 100MHz to 400MHz.
(4) 4.7pF capacitive load with a 5in trace
(5) All power supply pins are tied together. 0.1µF capacitor placed close to each power supply pin. Apply 50mVpp ripple and measure the spur level at the clock output