SNAS862B April 2025 – October 2025 LMK3H0102-Q1
PRODUCTION DATA
Table 7-11 summarizes the default settings of the LMK3H0102TV3 and LMK3H0102TV1 at start-up for the four OTP pages. In I2C mode, the Page 0 settings are loaded. For a full list of every default register setting, see Device Registers.
| Parameter | OTP Page 0 | OTP Page 1 | OTP Page 2 | OTP Page 3 |
|---|---|---|---|---|
| VDD supply voltage |
3.3V (LMK3H0102TV3) 1.8V (LMK3H0102TV1) |
|||
| OUT0 Frequency | 100MHz | 100MHz | 100MHz | 100MHz |
| OUT0 Output Format | 100Ω LP-HCSL | 100Ω LP-HCSL | 100Ω LP-HCSL | 100Ω LP-HCSL |
| OUT0 Enable | Enable | Enable | Enable | Enable |
| OUT0 Differential Slew Rate | 2.3V/ns to 3.5V/ns | 2.3V/ns to 3.5V/ns | 2.3V/ns to 3.5V/ns | 2.3V/ns to 3.5V/ns |
| OUT0 LP-HCSL Amplitude | 755mV (typical) | 755mV (typical) | 755mV (typical) | 755mV (typical) |
| OUT0_P/N Disable Behavior | Low/Low | Low/Low | Low/Low | Low/Low |
| OUT1 Frequency | 100MHz | 100MHz | 100MHz | 100MHz |
| OUT1 Output Format | 100Ω LP-HCSL | 100Ω LP-HCSL | 100Ω LP-HCSL | 100Ω LP-HCSL |
| OUT1 Enable | Enable | Enable | Enable | Enable |
| OUT1 Differential Slew Rate | 2.3V/ns to 3.5V/ns | 2.3V/ns to 3.5V/ns | 2.3V/ns to 3.5V/ns | 2.3V/ns to 3.5V/ns |
| OUT1 LP-HCSL Amplitude | 755mV (typical) | 755mV (typical) | 755mV (typical) | 755mV (typical) |
| OUT1_P/N Disable Behavior | Low/Low | Low/Low | Low/Low | Low/Low |
| REF_CTRL Behavior | CLK_READY | CLK_READY | CLK_READY | CLK_READY |
| FOD0 Frequency | 200MHz | 200MHz | 200MHz | 200MHz |
| FOD1 Frequency | 200MHz | 200MHz | 200MHz | 200MHz |
| SSC Enable | Disable | Enable | Enable | Enable |
| SSC Modulation Type | N/A | Down-spread | Down-spread | Down-spread |
| SSC Modulation Depth | N/A | -0.1% | -0.3% | -0.5% |
| Pin 2 Function |
Separate Output Enable |
Separate Output Enable |
Separate Output Enable |
Separate Output Enable |