SNAS862B April   2025  – October 2025 LMK3H0102-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. Parameter Measurement Information
    1. 6.1 Output Format Configurations
    2. 6.2 Differential Voltage Measurement Terminology
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA0]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3066]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x4000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0x6800]
      14. 8.1.14 R146 Register (Address = 0x92) [reset = 0x0000]
      15. 8.1.15 R147 Register (Address = 0x93) [reset = 0x0000]
      16. 8.1.16 R148 Register (Address = 0x94) [reset = 0x0000]
      17. 8.1.17 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Example: Changing Output Frequency
        2. 9.2.3.2 Crosstalk
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Device Default Settings

Table 7-11 summarizes the default settings of the LMK3H0102TV3 and LMK3H0102TV1 at start-up for the four OTP pages. In I2C mode, the Page 0 settings are loaded. For a full list of every default register setting, see Device Registers.

Table 7-11 LMK3H0102-Q1 Start-up Settings
ParameterOTP Page 0OTP Page 1OTP Page 2OTP Page 3
VDD supply voltage

3.3V (LMK3H0102TV3)

1.8V (LMK3H0102TV1)

OUT0 Frequency100MHz100MHz100MHz100MHz
OUT0 Output Format 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL
OUT0 EnableEnableEnableEnableEnable
OUT0 Differential Slew Rate2.3V/ns to 3.5V/ns2.3V/ns to 3.5V/ns2.3V/ns to 3.5V/ns2.3V/ns to 3.5V/ns
OUT0 LP-HCSL Amplitude755mV (typical)755mV (typical)755mV (typical)755mV (typical)
OUT0_P/N Disable BehaviorLow/LowLow/LowLow/LowLow/Low
OUT1 Frequency100MHz100MHz100MHz100MHz
OUT1 Output Format 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL
OUT1 EnableEnableEnableEnableEnable
OUT1 Differential Slew Rate2.3V/ns to 3.5V/ns2.3V/ns to 3.5V/ns2.3V/ns to 3.5V/ns2.3V/ns to 3.5V/ns
OUT1 LP-HCSL Amplitude755mV (typical)755mV (typical)755mV (typical)755mV (typical)
OUT1_P/N Disable BehaviorLow/LowLow/LowLow/LowLow/Low
REF_CTRL BehaviorCLK_READYCLK_READYCLK_READYCLK_READY
FOD0 Frequency200MHz200MHz200MHz200MHz
FOD1 Frequency200MHz200MHz200MHz200MHz
SSC EnableDisableEnableEnableEnable
SSC Modulation TypeN/ADown-spreadDown-spreadDown-spread
SSC Modulation DepthN/A-0.1%-0.3%-0.5%
Pin 2 Function

Separate Output Enable

Separate Output Enable

Separate Output Enable

Separate Output Enable