SNAS927 August   2025 LMKDB1202 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Synchronous OE
        2. 8.3.3.2 OE Control
          1. 8.3.3.2.1 OE Mapping
        3. 8.3.3.3 Automatic Output Disable
        4. 8.3.3.4 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Output Banks
        2. 8.3.4.2 Double Termination
        3. 8.3.4.3 Programmable Output Slew Rate
          1. 8.3.4.3.1 Slew Rate Control Through SMBus
        4. 8.3.4.4 Programmable Output Swing
        5. 8.3.4.5 Accurate Output Impedance
        6. 8.3.4.6 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB12xx Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 LMKDB1204 4mm × 4mm VQFN Package 28 Pin Top View
Legend
CLOCK INPUTS CLOCK OUTPUTS POWER
GND LOGIC CONTROLS / STATUS NO CONNECT
Table 5-1 LMKDB1204 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME(2)(3) NO.
CLOCK INPUTS
CLKIN0_P 2 I Differential clock input 0.
CLKIN0_N 3 I
CLKIN1_P 5 I Differential clock input 1.
CLKIN1_N 6 I
CLOCK OUTPUTS
CLK0_P 23 O LP-HCSL differential clock output 0. No connect if unused.
CLK0_N 24 O
CLK1_P 20 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N 21 O
CLK2_P 13 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N 14 O
CLK3_P 10 O LP-HCSL differential clock output 0. No connect if unused.
CLK3_N 11 O
POWER
VDDA 18 P Analog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDD_IN0 4 P Power supply for CLKIN0
VDD_IN1 7 P Power supply for CLKIN1
VDD_DIG 26 P Power supply for digital
VDDO_BANK1 12 P Power supply for output bank 1 (OUT4 to OUT7).
VDDO_BANK0 22 P Power supply for output bank 0 (OUT0 to OUT3).
GND 27 G Device Ground.
Thermal Pad (GND) Pad G Device Ground, Thermal pad.
LOGIC CONTROLS / STATUS
^OE0# 25 I Active low input to control CLK0. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive
^OE1# 19 I Active low input to control CLK1. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive
^OE2# 16 I Active low input to control CLK2. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive
^OE3#/SMB_CLK 9 I Output Enable for CLK3 Active Low/SMBus Clock. Internal pullup resistor. Functionality is decided by the state of pin 15 (SMB_EN) at power-up. When used as SMBus Clock pin, external pullup resistor is required. No connect if unused.
^vCLKIN_SEL_tri/SMB_DATA 8 I 3-Level Clock Input Select/SMBus Data. Internal pullup and pulldown resistor. Functionality is decided by the state of pin 15 (SMB_EN) at power-up.

When used as CLKIN_SEL_tri pin:

Low = CLKIN0 goes to all outputs

Mid = CLKIN0 goes to Bank 0, CLKIN1 goes to Bank 1

High = CLKIN1 goes to all outputs

When used as SMBus Data pin, external pullup resistor is required.
vPWRGD/PWRDN# 1 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode
vSMB_EN 15 I SMBus Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SMBus disabled. Pin 8 is CLKIN_SEL_tri and Pin 9 is OE3#.

High at power-up = SMBus enabled. Pin 8 is SMB_DATA and Pin 9 is SMB_CLK.
vZOUT_SEL 28 I LP-HCSL differential clock output impedance select. Internal pulldown resistor.

Low = 85Ω.

High = 100Ω.
LOS# 17 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating. Pins with "^/v" have an internal pullup or pulldown based on selected function.
(3) The "#" symbol indicates active low.
Figure 5-2 LMKDB1202 3mm × 3mm VQFN Package20 PinTop View
Legend
CLOCK INPUTS CLOCK OUTPUTS POWER
GND LOGIC CONTROLS / STATUS NO CONNECT
Table 5-2 LMKDB1202 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME(2)(3) NO.
CLOCK INPUTS
CLKIN0_P 1 I Differential clock input 0.
CLKIN0_N 2 I
CLKIN1_P 4 I Differential clock input 1.
CLKIN1_N 5 I
CLOCK OUTPUTS
CLK1_P 16 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N 17 O
CLK2_P 9 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N 10 O
POWER
VDD 14 P Analog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDD_IN0 3 P Power supply for CLKIN0
VDD_IN1 6 P Power supply for CLKIN1
VDD_DIG 19 P Power supply for digital
VDDO_BANK1 8 P Power supply for output bank 1.
VDDO_BANK0 18 P Power supply for output bank 0.
GND 20 G Device Ground.
Thermal Pad (GND) Pad G Device Ground, Thermal pad.
LOGIC CONTROLS / STATUS
^OE1# 15 I Active low input to control CLK1. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive
^OE2# 12 I Active low input to control CLK2. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive
^vCLKIN_SEL_tri 7 I 3-Level clock input select. Internal pullup and pulldown resistor.

Low = CLKIN0 goes to all outputs

Mid = CLKIN0 goes to Bank 0, CLKIN1 goes to Bank 1

High = CLKIN1 goes to all outputs
vZOUT_SEL 11 I LP-HCSL differential clock output impedance select. Internal pulldown resistor.

Low = 85Ω.

High = 100Ω.
LOS# 13 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating. Pins with "^/v" have an internal pullup or pulldown based on selected function.
(3) The "#" symbol indicates active low.