SNAU266A
July 2021 – August 2022
Abstract
1
First-Time Setup
1.1
Evaluation Module Contents
1.2
Evaluation Setup Requirements
2
EVM Connections
2.1
Connection Diagram
2.2
Power Supply
2.3
Reference Clock
2.4
Output Connections
2.5
Programming Interface
3
Feature Evaluation
3.1
Buffer, Divider, and Multiplier Modes
3.2
SYSREF Generation
3.3
SYSREF Delay Generators
4
Schematic
5
PCB Layout and Layer Stack-Up
5.1
PCB Layer Stack-Up
5.2
PCB Layout
6
Bill of Materials
A Troubleshooting
B USB2ANY Firmware Upgrade
C Revision History
5.2
PCB Layout
Figure 5-2
PCB Layer Plot - Top Layer
Figure 5-3
PCB Layer Plot - Layer 2 (RF GND)
Figure 5-4
PCB Layer Plot - Layer 3 (Signal GND 1)
Figure 5-5
PCB Layer Plot - Layer 4 (Signal GND 2)
Figure 5-6
PCB Layer Plot - Layer 5 (GND)
Figure 5-7
PCB Layer Plot - Bottom Layer