SNAU290 November   2024 LMK3H0102

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Critical Configuration Settings Overview
    1. 2.1 LMK3H0102Axxx Critical Device Settings
  6. 3OTP Page Configuration Overview
    1. 3.1 LMK3H0102Axxx OTP Page Configurations
  7. 4LMK3H0102Axxx Configuration Registers
    1. 4.1 LMK3H0102A001 Registers
      1. 4.1.1  LMK3H0102A001 R0 Register (Address = 0x0) [reset = 0x0863]
      2. 4.1.2  LMK3H0102A001 R1 Register (Address = 0x1) [reset = 0x5599]
      3. 4.1.3  LMK3H0102A001 R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 4.1.4  LMK3H1002A001 R3 Register (Address = 0x3) [reset = 0x1801]
      5. 4.1.5  LMK3H0102A001 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.1.6  LMK3H0102A001 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.1.7  LMK3H0102A001 R6 Register (Address = 0x6) [reset = 0x0AB8]
      8. 4.1.8  LMK3H0102A001 R7 Register (Address = 0x7) [reset = 0x2461]
      9. 4.1.9  LMK3H0102A001 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.1.10 LMK3H0102A001 R9 Register (Address = 0x9) [reset = 0x4036]
      11. 4.1.11 LMK3H0102A001 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.1.12 LMK3H0102A001 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.1.13 LMK3H0102A001 R12 Register (Address = 0xC) [reset = 0xE800]
    2. 4.2 LMK3H0102A006 Registers
      1. 4.2.1  LMK3H0102A006 R0 Register (Address = 0x0) [reset = 0x0489]
      2. 4.2.2  LMK3H0102A006 R1 Register (Address = 0x1) [reset = 0x2199]
      3. 4.2.3  LMK3H0102A006 R2 Register (Address = 0x2) [reset = 0xC71C]
      4. 4.2.4  LMK3H1002A006 R3 Register (Address = 0x3) [reset = 0x1903]
      5. 4.2.5  LMK3H0102A006 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.2.6  LMK3H0102A014 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.2.7  LMK3H0102A006 R6 Register (Address = 0x6) [reset = 0x8AA7]
      8. 4.2.8  LMK3H0102A006 R7 Register (Address = 0x7) [reset = 0x579F]
      9. 4.2.9  LMK3H0102A006 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.2.10 LMK3H0102A006 R9 Register (Address = 0x9) [reset = 0xD066]
      11. 4.2.11 LMK3H0102A006 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.2.12 LMK3H0102A006 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.2.13 LMK3H0102A006 R12 Register (Address = 0xC) [reset = 0xE800]
    3. 4.3 LMK3H0102A014 Registers
      1. 4.3.1  LMK3H0102A014 R0 Register (Address = 0x0) [reset = 0x0861]
      2. 4.3.2  LMK3H0102A014 R1 Register (Address = 0x1) [reset = 0x5599]
      3. 4.3.3  LMK3H0102A014 R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 4.3.4  LMK3H1002A014 R3 Register (Address = 0x3) [reset = 0x1801]
      5. 4.3.5  LMK3H0102A014 R4 Register (Address = 0x4) [reset = 0x0001]
      6. 4.3.6  LMK3H0102A014 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.3.7  LMK3H0102A014 R6 Register (Address = 0x6) [reset = 0x0AA0]
      8. 4.3.8  LMK3H0102A014 R7 Register (Address = 0x7) [reset = 0x6403]
      9. 4.3.9  LMK3H0102A014 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.3.10 LMK3H0102A014 R9 Register (Address = 0x9) [reset = 0x4866]
      11. 4.3.11 LMK3H0102A014 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.3.12 LMK3H0102A014 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.3.13 LMK3H0102A014 R12 Register (Address = 0xC) [reset = 0xE800]
    4. 4.4 LMK3H0102A015 Registers
      1. 4.4.1  LMK3H0102A015 R0 Register (Address = 0x0) [reset = 0x0861]
      2. 4.4.2  LMK3H0102A015 R1 Register (Address = 0x1) [reset = 0x5599]
      3. 4.4.3  LMK3H0102A015 R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 4.4.4  LMK3H1002A015 R3 Register (Address = 0x3) [reset = 0x1801]
      5. 4.4.5  LMK3H0102A015 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.4.6  LMK3H0102A015 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.4.7  LMK3H0102A015 R6 Register (Address = 0x6) [reset = 0x0AA1]
      8. 4.4.8  LMK3H0102A015 R7 Register (Address = 0x7) [reset = 0x1507]
      9. 4.4.9  LMK3H0102A015 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.4.10 LMK3H0102A015 R9 Register (Address = 0x9) [reset = 0x5066]
      11. 4.4.11 LMK3H0102A015 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.4.12 LMK3H0102A015 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.4.13 LMK3H0102A015 R12 Register (Address = 0xC) [reset = 0xE800]
    5. 4.5 LMK3H0102A016 Registers
      1. 4.5.1  LMK3H0102A016 R0 Register (Address = 0x0) [reset = 0x00C1]
      2. 4.5.2  LMK3H0102A016 R1 Register (Address = 0x1) [reset = 0xAB99]
      3. 4.5.3  LMK3H0102A016 R2 Register (Address = 0x2) [reset = 0x84EA]
      4. 4.5.4  LMK3H1002A016 R3 Register (Address = 0x3) [reset = 0x3001]
      5. 4.5.5  LMK3H0102A016 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.5.6  LMK3H0102A016 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.5.7  LMK3H0102A016 R6 Register (Address = 0x6) [reset = 0x1566]
      8. 4.5.8  LMK3H0102A016 R7 Register (Address = 0x7) [reset = 0x241D]
      9. 4.5.9  LMK3H0102A016 R8 Register (Address = 0x8) [reset = 0x84EA]
      10. 4.5.10 LMK3H0102A016 R9 Register (Address = 0x9) [reset = 0x6066]
      11. 4.5.11 LMK3H0102A016 R10 Register (Address = 0xA) [reset = 0x0810]
      12. 4.5.12 LMK3H0102A016 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.5.13 LMK3H0102A016 R12 Register (Address = 0xC) [reset = 0xE800]

3.1 LMK3H0102Axxx OTP Page Configurations

Any table entries below that are merged between OTP Pages are not able to be changed between OTP Pages.

Table 3-1 LMK3H0102A001 OTP Configuration
Parameter OTP Page 0 OTP Page 1 OTP Page 2 OTP Page 3
VDD Voltage 1.8V
OUT0 FOD Source FOD0
OUT0 Frequency 100MHz
OUT0 Output Format 100Ω LP-HCSL LVCMOS, Differential LVCMOS, Differential LVCMOS, Differential
OUT0 Enable Disabled Enabled Enabled Enabled
OUT0 Differential Slew Rate 1.4V/ns to 2.7V/ns
OUT0 LP-HCSL Amplitude 755mV
OUT0 Disable Behavior GND
OUT1 FOD Source FOD0
OUT1 Frequency 100MHz
OUT1 Output Format 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL
OUT1 Enable Disabled Enabled Enabled Enabled
OUT1 Differential Slew Rate 1.4V/ns to 2.7V/ns
OUT1 LP-HCSL Amplitude 690mV
OUT1 Disable Behavior GND
REF_CTRL Frequency N/A
REF_CTRL Behavior High-Z
FOD0 Frequency 200MHz
FOD1 Frequency 200MHz
SSC Enable Disabled Enabled Enabled Disabled
SSC Modulation Type No SSC Preconfigured -0.5% Down-spread Preconfigured -0.3% Down-spread No SSC
Pin 2 Function I2C Address LSB Selection
Table 3-2 LMK3H0102A006 OTP Configuration
Parameter OTP Page 0 OTP Page 1 OTP Page 2 OTP Page 3
VDD Voltage 3.3V
OUT0 FOD Source FOD0
OUT0 Frequency 24MHz
OUT0 Output Format LVCMOS, In-Phase LVCMOS, In-Phase LVCMOS, In-Phase LVCMOS, In-Phase
OUT0 Enable Enabled Enabled Enabled Enabled
OUT0 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT0 LP-HCSL Amplitude 755mV
OUT0 Disable Behavior GND
OUT1 FOD Source FOD1
OUT1 Frequency 25MHz
OUT1 Output Format LVCMOS, In-Phase LVCMOS, In-Phase LVCMOS, In-Phase LVCMOS, In-Phase
OUT1 Enable Enabled Enabled Enabled Enabled
OUT1 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT1 LP-HCSL Amplitude 755mV
OUT1 Disable Behavior GND
REF_CTRL Frequency 50MHz
REF_CTRL Behavior REF_CLK
FOD0 Frequency 144MHz
FOD1 Frequency 200MHz
SSC Enable Disabled Disabled Disabled Disabled
SSC Modulation Type No SSC No SSC No SSC No SSC
Pin 2 Function I2C Address LSB Selection
Table 3-3 LMK3H0102A014 OTP Configuration
Parameter OTP Page 0 OTP Page 1 OTP Page 2 OTP Page 3
VDD Voltage 3.3V
OUT0 FOD Source FOD0
OUT0 Frequency 100MHz
OUT0 Output Format 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL
OUT0 Enable Enabled Disabled Enabled Enabled
OUT0 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT0 LP-HCSL Amplitude 755mV
OUT0 Disable Behavior GND
OUT1 FOD Source FOD0
OUT1 Frequency 100MHz
OUT1 Output Format 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL 100Ω LP-HCSL
OUT1 Enable Disabled Enabled Enabled Enabled
OUT1 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT1 LP-HCSL Amplitude 755mV
OUT1 Disable Behavior GND
REF_CTRL Frequency N/A
REF_CTRL Behavior CLK_READY
FOD0 Frequency 200MHz
FOD1 Frequency 200MHz
SSC Enable Enabled Enabled Disabled Enabled
SSC Modulation Type Preconfigured -0.5% Down-spread Preconfigured -0.5% Down-spread Preconfigured -0.5% Down-spread Preconfigured -0.5% Down-spread
Pin 2 Function I2C Address LSB Selection
Table 3-4 LMK3H0102A015 OTP Configuration
Parameter OTP Page 0 OTP Page 1 OTP Page 2 OTP Page 3
VDD Voltage 3.3V
OUT0 FOD Source FOD0
OUT0 Frequency 100MHz
OUT0 Output Format 85Ω LP-HCSL 85Ω LP-HCSL 85Ω LP-HCSL 85Ω LP-HCSL
OUT0 Enable Enabled Enabled Enabled Enabled
OUT0 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT0 LP-HCSL Amplitude 755mV
OUT0 Disable Behavior GND
OUT1 FOD Source FOD0
OUT1 Frequency 100MHz
OUT1 Output Format 85Ω LP-HCSL 85Ω LP-HCSL 85Ω LP-HCSL 85Ω LP-HCSL
OUT1 Enable Enabled Enabled Enabled Enabled
OUT1 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT1 LP-HCSL Amplitude 755mV
OUT1 Disable Behavior GND
REF_CTRL Frequency 50MHz
REF_CTRL Behavior GND
FOD0 Frequency 200MHz
FOD1 Frequency 200MHz
SSC Enable Disabled Enabled Enabled Enabled
SSC Modulation Type No SSC Preconfigured -0.1% Down-spread Preconfigured -0.3% Down-spread Preconfigured -0.5% Down-spread
Pin 2 Function I2C Address LSB Selection
Table 3-5 LMK3H0102A016 OTP Configuration
Parameter OTP Page 0 OTP Page 1 OTP Page 2 OTP Page 3
VDD Voltage 3.3V
OUT0 FOD Source FOD0
OUT0 Frequency 50MHz
OUT0 Output Format LVCMOS, In-Phase LVCMOS, P Only LVCMOS, P Only LVCMOS, P Only
OUT0 Enable Disabled Enabled Enabled Enabled
OUT0 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT0 LP-HCSL Amplitude 755mV
OUT0 Disable Behavior GND
OUT1 FOD Source FOD0
OUT1 Frequency 50MHz
OUT1 Output Format LVCMOS, In-Phase LVCMOS, P Only LVCMOS, N Only LVCMOS, In-Phase
OUT1 Enable Disabled Enabled Enabled Enabled
OUT1 Differential Slew Rate 2.3V/ns to 3.5V/ns
OUT1 LP-HCSL Amplitude 755mV
OUT1 Disable Behavior GND
REF_CTRL Frequency N/A
REF_CTRL Behavior High-Z
FOD0 Frequency 100MHz
FOD1 Frequency 100MHz
SSC Enable Disabled Disabled Disabled Disabled
SSC Modulation Type No SSC No SSC No SSC No SSC
Pin 2 Function I2C Address LSB Selection