SNAU290 November   2024 LMK3H0102

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Critical Configuration Settings Overview
    1. 2.1 LMK3H0102Axxx Critical Device Settings
  6. 3OTP Page Configuration Overview
    1. 3.1 LMK3H0102Axxx OTP Page Configurations
  7. 4LMK3H0102Axxx Configuration Registers
    1. 4.1 LMK3H0102A001 Registers
      1. 4.1.1  LMK3H0102A001 R0 Register (Address = 0x0) [reset = 0x0863]
      2. 4.1.2  LMK3H0102A001 R1 Register (Address = 0x1) [reset = 0x5599]
      3. 4.1.3  LMK3H0102A001 R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 4.1.4  LMK3H1002A001 R3 Register (Address = 0x3) [reset = 0x1801]
      5. 4.1.5  LMK3H0102A001 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.1.6  LMK3H0102A001 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.1.7  LMK3H0102A001 R6 Register (Address = 0x6) [reset = 0x0AB8]
      8. 4.1.8  LMK3H0102A001 R7 Register (Address = 0x7) [reset = 0x2461]
      9. 4.1.9  LMK3H0102A001 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.1.10 LMK3H0102A001 R9 Register (Address = 0x9) [reset = 0x4036]
      11. 4.1.11 LMK3H0102A001 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.1.12 LMK3H0102A001 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.1.13 LMK3H0102A001 R12 Register (Address = 0xC) [reset = 0xE800]
    2. 4.2 LMK3H0102A006 Registers
      1. 4.2.1  LMK3H0102A006 R0 Register (Address = 0x0) [reset = 0x0489]
      2. 4.2.2  LMK3H0102A006 R1 Register (Address = 0x1) [reset = 0x2199]
      3. 4.2.3  LMK3H0102A006 R2 Register (Address = 0x2) [reset = 0xC71C]
      4. 4.2.4  LMK3H1002A006 R3 Register (Address = 0x3) [reset = 0x1903]
      5. 4.2.5  LMK3H0102A006 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.2.6  LMK3H0102A014 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.2.7  LMK3H0102A006 R6 Register (Address = 0x6) [reset = 0x8AA7]
      8. 4.2.8  LMK3H0102A006 R7 Register (Address = 0x7) [reset = 0x579F]
      9. 4.2.9  LMK3H0102A006 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.2.10 LMK3H0102A006 R9 Register (Address = 0x9) [reset = 0xD066]
      11. 4.2.11 LMK3H0102A006 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.2.12 LMK3H0102A006 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.2.13 LMK3H0102A006 R12 Register (Address = 0xC) [reset = 0xE800]
    3. 4.3 LMK3H0102A014 Registers
      1. 4.3.1  LMK3H0102A014 R0 Register (Address = 0x0) [reset = 0x0861]
      2. 4.3.2  LMK3H0102A014 R1 Register (Address = 0x1) [reset = 0x5599]
      3. 4.3.3  LMK3H0102A014 R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 4.3.4  LMK3H1002A014 R3 Register (Address = 0x3) [reset = 0x1801]
      5. 4.3.5  LMK3H0102A014 R4 Register (Address = 0x4) [reset = 0x0001]
      6. 4.3.6  LMK3H0102A014 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.3.7  LMK3H0102A014 R6 Register (Address = 0x6) [reset = 0x0AA0]
      8. 4.3.8  LMK3H0102A014 R7 Register (Address = 0x7) [reset = 0x6403]
      9. 4.3.9  LMK3H0102A014 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.3.10 LMK3H0102A014 R9 Register (Address = 0x9) [reset = 0x4866]
      11. 4.3.11 LMK3H0102A014 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.3.12 LMK3H0102A014 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.3.13 LMK3H0102A014 R12 Register (Address = 0xC) [reset = 0xE800]
    4. 4.4 LMK3H0102A015 Registers
      1. 4.4.1  LMK3H0102A015 R0 Register (Address = 0x0) [reset = 0x0861]
      2. 4.4.2  LMK3H0102A015 R1 Register (Address = 0x1) [reset = 0x5599]
      3. 4.4.3  LMK3H0102A015 R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 4.4.4  LMK3H1002A015 R3 Register (Address = 0x3) [reset = 0x1801]
      5. 4.4.5  LMK3H0102A015 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.4.6  LMK3H0102A015 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.4.7  LMK3H0102A015 R6 Register (Address = 0x6) [reset = 0x0AA1]
      8. 4.4.8  LMK3H0102A015 R7 Register (Address = 0x7) [reset = 0x1507]
      9. 4.4.9  LMK3H0102A015 R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 4.4.10 LMK3H0102A015 R9 Register (Address = 0x9) [reset = 0x5066]
      11. 4.4.11 LMK3H0102A015 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 4.4.12 LMK3H0102A015 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.4.13 LMK3H0102A015 R12 Register (Address = 0xC) [reset = 0xE800]
    5. 4.5 LMK3H0102A016 Registers
      1. 4.5.1  LMK3H0102A016 R0 Register (Address = 0x0) [reset = 0x00C1]
      2. 4.5.2  LMK3H0102A016 R1 Register (Address = 0x1) [reset = 0xAB99]
      3. 4.5.3  LMK3H0102A016 R2 Register (Address = 0x2) [reset = 0x84EA]
      4. 4.5.4  LMK3H1002A016 R3 Register (Address = 0x3) [reset = 0x3001]
      5. 4.5.5  LMK3H0102A016 R4 Register (Address = 0x4) [reset = 0x0000]
      6. 4.5.6  LMK3H0102A016 R5 Register (Address = 0x5) [reset = 0x0000]
      7. 4.5.7  LMK3H0102A016 R6 Register (Address = 0x6) [reset = 0x1566]
      8. 4.5.8  LMK3H0102A016 R7 Register (Address = 0x7) [reset = 0x241D]
      9. 4.5.9  LMK3H0102A016 R8 Register (Address = 0x8) [reset = 0x84EA]
      10. 4.5.10 LMK3H0102A016 R9 Register (Address = 0x9) [reset = 0x6066]
      11. 4.5.11 LMK3H0102A016 R10 Register (Address = 0xA) [reset = 0x0810]
      12. 4.5.12 LMK3H0102A016 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 4.5.13 LMK3H0102A016 R12 Register (Address = 0xC) [reset = 0xE800]

4.2.11 LMK3H0102A006 R10 Register (Address = 0xA) [reset = 0x0010]

Table 4-24 R10 Register Field Descriptions
BitFieldTypeResetDescription
15ReservedR/W0x0Reserved. Only write '0' to this bit.
14:11PROD_REVIDR0x0Product revision identifier.
10CLK_READYR0x0CLK_READY status. The REF_CTRL pin mirrors this status signal when the pin functions as a "clock ready" signal.
9ReservedR0x0Reserved. Do not write to this field.
8RB_PIN_15R0x0Readback of the REF_CTRL pin.
7RB_PIN_4R0x0Readback of the OTP_SEL1/SDA pin.
6RB_PIN_3R0x0Readback of the OTP_SEL0/SCL pin.
5RB_PIN_2R0x0Readback of the FMT_ADDR pin.
4DEV_IDLE_STATE_SELR/W0x1

This bit controls the behavior of the device when both outputs are disabled. Placing the device into a low-power state is not recommended for PCIe applications, as the time to re-enable the clocks is extended. This field is stored in the EFUSE.

0h: When both outputs are disabled, the outputs are muted, and the device is placed into a low-power state.

1h: When both outputs are disabled, the outputs are muted. The device does not enter a low-power state.

3PIN_RESAMPLE_DISR/W0x0

This bit controls the resampling of the device pins when exiting the low power mode. Write this bit while in the low power mode. TI recommends keeping this bit as a '1' unless the functionality is explicitly desired. After PDN, pins 2, 3, 4, and 15 are resampled. Device functionality can change based on new logic level of the pins.

0h: Pin resampling is enabled. When exiting the low power mode, the FMT_ADDR, OTP_SEL0/SCL, OTP_SEL1/SDA, and FMT_ADDR pins are resampled. If FMT_ADDR is high, the device enters OTP Mode.

1h: Pin resampling is disabled. When exiting the low power mode, the FMT_ADDR, OTP_SEL0/SCL, OTP_SEL1/SDA, and FMT_ADDR pins are not resampled. The device remains in I2C Mode.

2OTP_AUTOLOAD_DISR/W0x0

This bit controls the behavior of the device when exiting the low power mode. Write this bit while in the low power mode. TI recommends keeping this bit as a '1' unless the functionality is explicitly desired.

0h: OTP autoload is enabled. When exiting the low power mode, the contents of OTP Page 0 are written to the device registers.

1h: OTP autoload is disabled. When exiting the low power mode, the contents of OTP Page 0 are not written to the device registers.

1PDNR/W0x0

Writing a '1' to this bit puts the device into a low power state.

0ReservedR/W0x0Reserved, do not write to this field.